Nvidia Corporation

Praveen Kaushik

Jack H Choquette

Manan Patel

Shirish C Gadre

Ajay Sudarshan Tirumala

Olivier Giroux

Michael Alan Fetterman

Robert Ohannessian

Ronny Krashinsky

Andrei Khodakovsky

Rishkul Kulkarni

Jeffery Michael Schottmiller

Ming Liang Milton Lei

Konstantinos Kyriakopoulos

Amanpreet Grewal

Aditya Avinash Atluri

Shekhar Vasant Divekar

Carter Edwards

Pritha Ghoshal

A first instruction to load a first data into a first register file associated with a first subpartition unit is received. A second instruction to load the first data into a second register file associated with a second subpartition unit is received. The first instruction and the second instruction are coalesced into a first entry of a request coalescer based on instruction identifiers. The first entry is associated with the first data. Responsive to a determination that the first data is available in the cache, the first data is multicast from the cache to the first register file and the second register file.

Systems and methods for multicasting data

Apparatuses, systems, and techniques to adapt instructions in a SIMT architecture for execution on serial execution units. In at least one embodiment, a set of one or more threads is selected from a group of active threads associated with an instruction and the instruction is executed for the set of one or more threads on a serial execution unit.

Scalarization of instructions for SIMT architectures

A just-in-time (JIT) compiler binds constants to specific memory locations at runtime. The JIT compiler parses program code derived from a multithreaded application and identifies an instruction that references a uniform constant. The JIT compiler then determines a chain of pointers that originates within a root table specified in the multithreaded application and terminates at the uniform constant. The JIT compiler generates additional instructions for traversing the chain of pointers and inserts these instructions into the program code. A parallel processor executes this compiled code and, in doing so, causes a thread to traverse the chain of pointers and bind the uniform constant to a uniform register at runtime. Each thread in a group of threads executing on the parallel processor may then access the uniform constant.

Binding constants at runtime for improved resource utilization

A compiler parses a multithreaded application into cohesive blocks of instructions. Cohesive blocks include instructions that do not diverge or converge. Each cohesive block is associated with one or more uniform registers. When a set of threads executes the instructions in a given cohesive block, each thread in the set may access the uniform register independently of the other threads in the set. Accordingly, the uniform register may store a single copy of data on behalf of all threads in the set of threads, thereby conserving resources.

Uniform register file for improved resource utilization

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Bengaluru, India

Praveen Kaushik