International Business Machines Corporation

Praveen Karandikar

James Norris Dieffenderfer

Thomas Philip Speier

Paul Michael Steinmetz

Michael B Mitchell

Eric Francis Robinson

Jason Alan Cox

Mark J Wolski

A method and system prevents accidental direction selection in a motor vehicle. The driver of the vehicle is alerted that the selected direction of the vehicle via the gear shift is opposite of the direction that the driver intends for the vehicle to move. The selected direction of the vehicle by the driver is initially detected. The invention then detects the driver's physical position and any objects in the immediate area surrounding the vehicle. Based on the information gathered from these detections, there is determination made regarding the vehicle direction selected by the driver. If the determination is the likelihood of an accident/collision if the vehicle moves in the selected direction, the present invention will alert the driver. In addition, an embodiment of the present invention may also include the ability to disable the vehicle in order to avoid a collision.

Method and system for detection of motor vehicle movement to avoid collisions

Methods, apparatuses, and computer program products are disclosed for cache management. Embodiments include receiving, by a cache controller, a request to insert a new cache line into a cache; determining, by the cache controller, whether the new cache line is associated with a forced injection; in response to determining that the new cache line is associated with a forced injection, accepting, by the cache controller, the insertion of the new cache line into the cache; and in response to determining that the new cache line is not associated with a forced injection, determining, by the cache controller, whether to accept the insertion of the new cache line based on a comparison of an address of the new cache line to a predefined range of addresses.

Managing unforced injections of cache lines into a cache utilizing predetermined address ranges

Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

Promoting a line from shared to exclusive in a cache

Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.

Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache

A method and apparatus are provided for determining power events on an I/C chip for undissipated power to the chip, and wherein the chip includes a plurality of separately regulatable power consumers. A structure is provided for monitoring the occurrence of each power event to each power consumer, and determining the dissipation of power from each power event, and controlling power used by the chip responsive to the amount of undissipated power.

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Cary, NC, United States of America

Praveen Karandikar