Analog Devices International Unlimited Company

Praveen Chandrasekaran

Stephen Summerfield

Christopher Mayer

Dong Chen

Mark Cope

Patrick Joseph Pratt

Anand Venkitasubramani

Bhavana Muralikrishna

Shreeja Sugathan

Kaustubh Pradeepkumar Mundhada

Vinoth Kumar Rajasekar

Naveen Naraharisetti

Chris Mayer

Systems and methods for compensating a transmit signal for charge trapping effects of a power amplifier are provided. In certain embodiments, a non-linear filter is trained based on time aligning a first set of observations taken from digital transmit data prior to conversion to a radio frequency transmit signal, and a second set of observations taken from an output of a power amplifier that amplifies the radio frequency transmit signal. In certain implementations, the first set of observations and the second set of observations are obtained without decimation. Rather, decimation is provided after timing alignment. By implementing the DPD system in this manner, signal data is not lost by decimation and more accurate timing alignment between the sets of observations is achieved.

Systems and methods of compensating a transmit signal for charge trapping effects of a power amplifier

Systems, devices, and methods related to performing digital predistortion in radio frequency (RF) systems are provided. A digital predistortion (DPD) arrangement includes a DPD actuator circuit to predistort, using DPD coefficients, at least a portion of an input signal, the DPD coefficients associated with a characteristic of a nonlinear component. The DPD arrangement further includes a DPD capture circuit to perform, based on a capture cycle timing, multiple captures of a feedback signal, the feedback signal indicative of an output of the nonlinear component; compute, based on one or more characteristics of the multiple captures, one or more criteria for a subsequent capture of the feedback signal; and perform, based on the one or more criteria, the subsequent capture of the feedback signal. The DPD arrangement circuit further includes a DPD adaptation circuit to update the DPD coefficients based at least in part on the subsequent capture.

Obtaining reliable and specific data for adaptive digital predistortion

Some embodiments herein describe a radio frequency communication system that can include a transmitter to output an radio frequency (RF) transmit signal, the transmitter including a digital pre-distortion system (DPD) that pre-distorts the RF transmit signal. The DPD system can include a configurable non-linear filter, such as a Laguerre filter, having multiple rows where at least one row operates with a configurable decimation ratio. The DPD system can further include decimators and a crossbar switch coupled between the decimators.

Configurable non-linear filter for digital pre-distortion

Systems, devices, and methods related to interpolation are provided. An example apparatus includes a slope calculator to calculate a slope value based on a first value and a second value associated with a function. The apparatus further includes a compander to compand the slope value to provide a companded slope value having a smaller bit-width than the calculated slope value. The apparatus further includes a multiplier to multiply the companded slope value by a third value to provide a correction value. The apparatus further includes an adder to add the correction value to the first value or the second value to provide an interpolated value associated with the function. Companding the slope value can reduce a bit-width of the multiplier, and thus may reduce power consumption and/or area.

Lookup table (LUT) interpolation with optimized multiplier width using companding in correction slope

A matrix multiplication circuit comprises a memory storage device, processing circuitry, a parallel multiply circuit, and buffer circuits. The parallel multiply circuit simultaneously performs a count of multiplies in a parallel multiplication operation. The buffer circuits include prefetch buffer circuits each having a storage array dimension corresponding to the count of multiplies in the parallel multiplication operation. The processing circuitry loads a first prefetch buffer circuit with values from the first matrix; fetches a value of the second matrix and, in parallel with the fetch, preload the second prefetch buffer circuit with another value from the first matrix; initiates a parallel multiply of the fetched value of the second matrix and the values in the first prefetch buffer circuit; and stores partial product results of the parallel multiply, including adding a current partial product result to a previously stored partial product result.

Parallel matrix multiplication technique optimized for memory fetches

Some embodiments herein describe a radio frequency power semiconductor device that include a first non-linear filter network for compensating for lower frequency noise of a power amplifier. The first non-linear filter network can include a plurality of infinite impulse response filters and corresponding corrective elements to correct for a non-linear portion of the power amplifier. The radio frequency power semiconductor device can further include a second non-linear filter network for compensating for broadband distortion. The second non-linear filter network can be connected in parallel to the first non-linear filter network. The broadband distortion can include digital predistortion and the narrowband distortion can include charge trapping effects. The first non-linear filter network can comprise Laguerre filters. The second non-linear filter network can comprise general memory polynomial filters.

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Bengaluru, India

Praveen Chandrasekaran