Intel Ndtm US LLC

Pratyush Chandrapati

Aliasgar S Madraswala

Shantanu R Rajwade

Sagar Upadhyay

Tarek Ahmed Ameen Beshari

Naveen Prabhu Vittal Prabhu

Ahsanur Rahman

Shanmathi Mookiah

A storage device charges bitlines in preparation for a program pulse. To charge the bitlines, the storage device connects the bitlines to an external regulator instead of an internal regulator to prepare them for the program pulse. The system can charge all bitlines to the external regulator high voltage reference before changing to the internal regulator for bitline stabilization before the program pulse.

Efficient bitline stabilization for program inhibit in NAND arrays

The size of page map memory in a NAND flash device used to store page related information is decreased by embedding page type in a row address. The row address is received by the NAND flash device from the host on the data bus in a six-cycle sequence. The received row address is used to decode a physical page address received during the row address cycle to obtain a word line and a block segment number for a block segment in the word line in the NAND flash array. A same block segment number is used for each page type in the block segment.

Method and apparatus to reduce memory in a NAND flash device to store page related information

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Folsom, CA, United States of America

Pratyush Chandrapati