National Semiconductor Corporation

Fairchild Semiconductor Corporation

Nexflash Technologies, Inc.

Silicon Storage Technology, Inc.

Prateep Tuntasood

Hieu Van Tran

Nhan Do

Xian Liu

Feng Zhou

Chien-Sheng Su

Jinho Kim

Reda R Razouk

Michael P Brassington

Yaw Wen Hu

Monir H El-Diwany

Parviz Ghazavi

Juliana Manoliu

Chien Sheng Su

A method for fabricating a tunnel window in an EEPROM cell that reduces or eliminates the initial active region overlap yet still compensates for tunnel window misalignment. The inventive method accomplishes this by removing a portion of the field oxide layer surrounding an initial active region before depositing the BN&plus; diffusion layer. This step is performed in order to enlarge the area in which the BN&plus; diffusion layer is formed to beyond the perimeter of the tunnel window forming a final active region. As a result, the method of the present invention ensures that the tunnel window is fully enclosed by the BN&plus; diffusion layer despite any tunnel window misalignment that may occur. Reducing the initial active region creates an EEPROM cell with a reduced cell pitch while increasing its coupling ratio.

Method for fabricating tunnel window in EEPROM cell with reduced cell pitch

A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process includes the fabrication of buried layers 18 doped with both phosphorus and arsenic to permit a shorter diffusion time while simultaneously providing buried layers having low resistance and high diffusivity. The process enables fabrication of BiCMOS structures using only six masks prior to the contact mask. The process also comprises oxidizing an epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions, the collector contact and the emitter than over the base contact region.

Method for simultaneously fabricating bipolar and complementary field

A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.

Method of manufacturing a polysilicon emitter and a polysilicon gate

Bipolar and MOS devices are made simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.

Polysilicon emitter and a polysilicon gate using the same etch of

A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process includes the fabrication of buried layers 18 doped with both phosphorus and arsenic to permit a shorter diffusion time while simultaneously providing buried layers having low resistance and high diffusivity. The process enables fabrication of BiCMOS structures using only six masks prior to the contact mask.

A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process enables distinguishing the bipolar devices from the CMOS devices with a single base mask 108, while requiring only a single additional mask 114 to define the bipolar emitter and MOS gates. The process forms the gate oxide 100 for the MOS devices at an early stage, then protects that oxide with polysilicon 103 during subsequent fabrication steps. Self-aligned metal silicide contacts 137 are separated from undesired regions using sidewall oxidation techniques.

Growing community of inventors

San Jose, CA, United States of America

Prateep Tuntasood