Silicon Storage Technology, Inc.

Actrans System Inc.

Actrans System Incorporation, USA

Prateep Tuntasood

Der-Tsyr Fan

Chiou-Feng Chen

Yaw Wen Hu

Ben Y Sheen

Jung-Chang Lu

Nhan Do

Bomy A Chen

Geeng-Chuan Chern

Chien-Sheng Su

Jonathan Pabustan

Ming-Jer Chen

Caleb Yu-Sheng Cho

Hieu Van Tran

Yuniarto Widjaja

Xian Liu

Feng Zhou

Jinho Kim

Parviz Ghazavi

Tseng-Yi Liu

Henry A O'M'Mani

A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.

Method of forming memory array and logic devices

A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.

Non-volatile memory cells with enhanced channel region effective width, and method of making same

A non-volatile memory cell has a substrate layer with a fin shaped semiconductor member of a first conductivity type on the substrate layer. The fin shaped member has a first region of a second conductivity type and a second region of the second conductivity type, spaced apart from the first region with a channel region extending between the first region and the second region. The fin shaped member has a top surface and two side surfaces between the first region and the second region. A word line is adjacent to the first region and is capacitively coupled to the top surface and the two side surfaces of a first portion of the channel region. A floating gate is adjacent to the word line and is insulated from the top surface and is capacitively coupled to the two side surfaces of a second portion of the channel region. A coupling gate is capacitively coupled to the floating gate. An erase gate is insulated from the second region and is adjacent to the floating gate and coupling gate.

FIN-FET non-volatile memory cell, and an array and method of manufacturing

A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates ('first alternating gates'). In addition, a ground voltage is applied to erase gates other than the first alternating gates ('second alternating gates'). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.

Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio

A plurality of non-volatile memory cell units are arranged in rows and columns in a single crystalline semiconductor substrate of a first conductivity type. Each cell unit has a first region of a second conductivity type in the substrate along the planar surface, and a second region of the second conductivity, spaced apart from the first region, with a channel region therebetween. The channel region has a first portion adjacent to the first region, a third portion adjacent to the second region and a second portion therebetween. A first and second floating gates are over the first portion and third portion respectively and are insulated therefrom. A first and second control gates are over the first and second floating gates respectively and are capacitively coupled thereto. A first and second erase gates are over the first and second regions respectively and are insulated therefrom. A word line is over the second portion and is insulated therefrom. Electrical contacts to the array are made along the extremities of the array.

Array of contactless non-volatile memory cells

Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Process of fabricating flash memory with enhanced program and erase coupling

NAND flash memory cell array having control gates and charge storage gates stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other, and the charge storage gates are either a nitride or a combination of nitride and oxide. Programming is done by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates. Erasing is done by channel tunneling from the charge storage gates to the silicon substrate or by hot hole injection from the silicon substrate to the charge storage gates. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

NAND flash memory with nitride charge storage gates and fabrication process

Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates beside the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate, and at least one additional conductor capacitively coupled to the floating gates. In some disclosed embodiments, the conductors adjacent to the bit line diffusions are word lines, and the additional conductors consist of either a pair of coupling gates which are coupled to respective ones of the floating gates or a single coupling gate which is coupled to both of the floating gates. In another embodiment, the conductors adjacent to the bit line diffusions are program lines, and the third conductors are word lines which extend in a direction perpendicular to the program lines and the diffusions.

NOR flash memory

NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

NAND flash memory with densely packed memory gates and fabrication process

Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

Self-aligned split-gate NAND flash memory and fabrication process

A memory array has a plurality of memory cells, arranged in a plurality of rows and columns. Each cell has at least four terminals. The array has a plurality of column lines with each column line connected to a first terminal of a different column of cells. The array also has a plurality of first row lines, with each first row line connected to a second terminal of a different row of cells. The array also has a plurality of second row lines, with each second row line connected to a third terminal of a different row of cells. Finally, the array has a plurality of third row lines with each third row line connected to a fourth terminal of a different row of cells. A column decoder is connected to the plurality of column lines. A first row decoder is connected to the plurality of first row lines. A second row decoder is connected to the plurality of second row lines. A third row decoder is connected to the plurality of third row lines. During an operation of a selected cell, the column decoder selects one of the plurality of column lines, with the one column line selected connected to the first terminal of the selected cell. The first row decoder selects one of the plurality of first row lines with the one first row line selected connected to the second terminal of the selected cell. The second row decoder selects a first plurality of second row lines, with one of the first plurality of second row lines connected to the third terminal of the selected cell. The third row decoder selects a second plurality of third row lines, with one of the second plurality of third row lines connected to the fourth terminal of the selected cell. Finally, the first plurality of second row lines, other than the one second row line, are connected to cells arranged in rows other than rows of cells to which the second plurality of third row lines are connected. The interconnection minimizes programming disturbance.

Method and apparatus for reducing operation disturbance

Flash memory with enhanced program and erase coupling and process of fabricating the same

Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.

Growing community of inventors

Santa Clara, CA, United States of America

Prateep Tuntasood