Apple Inc.

Micron Technology Incorporated

Brocade Communication Systems LLC

Prateek Sharma

Deepankar Bhattacharjee

Sreevalsan Vallath

Raja V S Halaharivi

Sanjay K Verma

Yoav Weinberg

Swaminathan Balakrishnan

Venkat R Gaddam

Sumangal Chakrabarty

Bridget L Mallak

Tianyan Pu

Scheheresade Virani

Aleksei Vlasov

Dawei Zhang

Wei Zeng

Haitong Sun

Wei Zhang

Vijay Venkataraman

Haijing Hu

Sarma V Vangala

Ping Wang

Farouk Belghoul

Sami M Almalfouh

Ajoy K Singh

Rohan C Malthankar

Michael Jason Giles

Horia Cristian Simionescu

Najeeb M Abdulrahiman

Cesar Perez

Craig P Dooley

Daniel R Borges

Kevin R Duncan

Surya Parkash Varanasi

Adesh Kumar

Tony Nguyen

Sairam T Gutta

Di Hsien Ngu

Gregory S Walter

A system includes host interface circuitry to interact with a host system and that includes an address translation circuit, which includes request staging queues to buffer the address translation requests, each includes a virtual address and received from a host interface circuit. Pending response queues buffer respective address translation requests that are waiting for an address translation from the host system while maintaining an order as received within the request stage queues. Reordering buffers reorder address translations, which are to be supplied to the host interface circuits, according to the order maintained within the pending response queues, each address translation includes a physical address mapped to the virtual address of a corresponding address translation request. A cache stores multiple of the address translations, associated with the address translation requests, for future access by the host interface circuits.

Caching host memory address translation data in a memory sub-system

In some implementations, a memory device may obtain, from a host device, a first one or more commands associated with a first identifier. The memory device may maintain a first counter associated with tracking active commands from the host device. The memory device may detect an event, associated with a command, at a first time. The memory device may switch, based on detecting the event, an active identifier for commands obtained after the first time to a second identifier. The memory device may initiate a second counter associated with tracking active commands that were obtained prior to the first time. The memory device may perform an action associated with a command that is associated with the first identifier. The memory device may update, based on performing the action, the first counter and the second counter based on the at least one command being associated with the first identifier.

Memory device active command tracking

A processing device includes host interface circuitry to interact with a host system and an address translation circuit to handle address translation requests to the host system from host interface circuits. The address translation circuit includes a cache to store address translations associated with the address translation requests for future access by host interface circuits. A page request interface (PRI) handler tracks translation miss messages received from the host interface circuits, each translation miss message including a virtual address of a miss at the cache. The PRI handler removes duplicate translation miss messages having an identical virtual address and creates page miss requests from non-duplicate translation miss messages that are categorized into page request groups, each page request group corresponding to a host interface circuit of the host interface circuits. The PRI handler queues the page request groups to be sent to a translation agent of the host system.

Page request interface (PRI) handler operational support in relation to caching host memory address translation data in a memory sub-system

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving, from a host system, a memory access command; executing the memory access command; identifying a characteristic associated with the memory access command; identifying a threshold period of time corresponding to the characteristic associated with the memory access command; determining that a period of time associated with the memory access command satisfies the threshold period of time; and responsive to determining that the period of time associated with the memory access command satisfies the threshold period of time, notifying the host system of completion of execution of the memory access command.

Managing command completion notification pacing in a memory sub-system

A device includes an address translation circuit of host interface circuitry to handle address translation requests to a host system from a host queue interface circuit. The address translation circuit includes cache to store address translations associated with the address translation requests. The host queue interface circuit, coupled to the address translation circuit, is to: pause command fetch arbitration on a submission queue of the host system that is targeted by an address translation request that missed at the cache; trigger a page request interface (PRI) handler to send a page miss request to a translation agent (TA) of the host, the page miss request including a virtual address of the address translation request; receive a restart message from the PRI handler upon the PRI handler receiving a page miss response from the TA; and restart command arbitration on the submission queue that was paused responsive to the restart message.

Page request interface support in handling host submission queues and completion automation associated with caching host memory address translation data

A system includes a memory device, a first interface port and a second interface port operatively coupled with the memory device, and a processing device, operatively coupled with the memory device, to perform operations including: detecting a triggering event associated with the first interface port; responsive to detecting the triggering event, sending an interrupt message to a firmware component of the memory device; receiving, from the firmware component, a configuration setting based on the interrupt message; and allocating, by the processing device, one or more resources to the first interface port according to the configuration setting.

Balancing performance between interface ports in a memory sub-system

A user equipment (UE) is configured with a carrier aggregation (CA) functionality and UE connected to a network via a base station that serves as a primary serving cell (PCell) providing a primary component carrier (PCC) to the UE. The UE determines a plurality of bands that are supported by the UE for use in the CA functionality, generates an individual band information element (IE) including band information for the bands, determines at least one representative CA combination having an order, the order indicating a total number of component carriers (CCs), the at least one representative CA combination forming a basis to extrapolate a plurality of CA combinations having the order based on the band information, generates a representative CA combination IE including the at least one representative CA combination and transmits the individual band IE and the representative CA combination IE to the base station.

Carrier aggregation capability advertisement

A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.

Data packet management

A processing device of a memory sub-system can receive a plurality of commands from a plurality of virtual machines via a host interface and associate each of the plurality of commands with a respective function that represents a respective virtual machine from which each of the plurality of commands was received. The controller of the memory sub-system can also setup a respective definition of a respective quality of service for each respective function regarding consumption of resources of the memory device, wherein the controller comprises arbitration circuitry to handle each of the plurality of commands on a per function basis according to the definition.

Function arbitration and quality of service for memory commands

A processing device of a memory sub-system can receive a first address from a host and can provide the first address to a memory management unit (MMU) for translation. The processing device can also receive a second address from the MMU wherein the second address is translated from the first address. The processing device can further access the memory device utilizing the second address.

User process identifier based address translation

This disclosure relates to providing a reservation signal for cellular communication in unlicensed spectrum. A cellular base station may perform a listen-before-talk procedure on an unlicensed frequency channel. The cellular base station may transmit a reservation signal on the unlicensed frequency channel after successfully performing the listen-before-talk procedure. The cellular base station may perform carrier sensing on the unlicensed frequency channel at least once during the duration of the reservation signal. The cellular base station may perform cellular communication on the unlicensed frequency channel after ceasing transmitting the reservation signal.

Enhanced reservation signal for cellular communication in unlicensed spectrum

An apparatus, method and system for receiving an input indicating a mode into which to set a user equipment (UE) and at least one further UE associated with the UE, determining whether a connection circuit switched (CS) connectivity or packet switched (PS) connectivity and when the connection is the CS connectivity, generating a short messaging service (SMS) message that indicates the mode corresponding to the input. Also, receiving connectivity information for a plurality of UEs from a cloud network component, the UEs being associated with one another, the connectivity being CS connectivity or PS connectivity, receiving a response indication corresponding to a response performed on an incoming call by a first one of the UEs, the first UE having a PS connectivity, matching the response indication to a corresponding cause code and transmitting the corresponding cause code to a second one of the UEs having a CS connectivity.

Device, system and method for synchronizing multiple devices

A user equipment and a method performed by the user equipment that has a transceiver configured to enable the user equipment to establish a connection with a first network and a second network. The method including establishing a connection to each of the first network and the second network, tuning away from the first network to the second network, tuning back to the first network from the second network and determining whether to perform a network operation with the first network after tuning back to the first network.

Apparatus, system and method for optimized tune away procedures

Growing community of inventors

San Jose, CA, United States of America

Prateek Sharma