Advanced Micro Devices Corporation

Prateek Mishra

Girish Anathahalli Singrigowda

Jagadeesh Anathahalli Singrigowda

Animesh Jain

Dhruvin Devangbhai Shah

Thanapandi Ganesan

Thanapandi G

A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (I/O) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.

High to low level shifter architecture using lower voltage devices

A level shifting output circuit converts a signal from a core voltage to an I/O voltage without causing voltage overstress on transistor terminals in the level shifting output circuit. The output circuit includes protection transistors to protect various transistors in the output circuit from overvoltage conditions including those transistors coupled to I/O power supply nodes.

Level shifting output circuit

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Uttar Pradesh, India

Prateek Mishra