Cadence Design Systems, Inc.

Prateek Kumar Rai

Krishna Chakravadhanula

Sarthak Singhal

Vivek Chickermane

Brian Edward Foutz

Christos Papameletis

Bharath Nandakumar

A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that divide the test-point nodes into a plurality of test-point sharing groups in which each of the test-point nodes is associated with one of the clock-gates that is common to each of at least one flip-flop of the portion of the functional logic coupled to each of the respective test-point nodes in the test-point sharing group. The test-point flop allocation module can further allocate one of the test-point flops to each of the test-point sharing groups. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design based on the circuit netlist. The circuit layout is employable to fabricate an IC chip.

Clock-based test-point flop sharing in a circuit design

A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.

Test-point flop sharing with improved testability in a circuit design

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Uttar Pradesh, India

Prateek Kumar Rai