Vmware, Inc.

Other

Hewlett-packard Development Company, L.p.

Pratap Subrahmanyam

Rajesh Venkatasubramanian

Carl Alan Waldspurger

Irina Calciu

Marcos Kawazoe Aguilera

Xiaoxin Chen

Daniel J Scales

Andreas Georg Nowatzyk

Michael Nelson

Kiran Tati

Jayneel Gandhi

Venkata Subhash Reddy Peddamallu

Aasheesh Kolli

Ole Agesen

Keerthi B Kumar

Xavier Deguillard

Pramod Kumar

Isam Wadih Akkawi

Qasim Ali

Tal Garfinkel

Sairam Veeraswamy

Zongwei Zhou

Bich Cau Le

Ganesh Venkitachalam

Dragutin Petkovic

Dilip Khandekar

Dan Boneh

Garrett Cale Smith

Daniel R K Ports

Adarsh Seethanadi Nayak

Yi Yao

Nishchay Dua

Keith Adams

Vyacheslav Vladimirovich Malyugin

Scott W Devine

Oded Horovitz

Raviprasad V Mummidi

Praveen Vegulla

Mendel Rosenblum

Dmitriy Budko

Emmanuel Amaro Ramirez

Wei Xu

Michael Wei

Sahil Rihan

Edouard Bugnion

Nadav Amit

Eric Schkufza

Doug Covelli

Lalith Suresh

Vijaychidambaram Velayudhan Pillai

Richard Brunner

Stanko Novakovic

Nathaniel McIntosh

Manish Mishra

Himanshu Chauhan

Onur Mutlu

Edouard Bugnlon

Yizhou Shan

Arun Ramanathan

Renu Raman

Disclosed are various embodiments for optimizing the migration of pages of memory servers in cluster memory systems. To begin, a computing device can mark in a page table of the computing device that a page stored on a first memory host is not present. Then, the computing device can flush a translation lookaside buffer of the computing device. Next, the computing device can copy the page from the first memory host to a second memory host. Moving on, the computing device can update a page mapping table to reflect that the page is stored in the second memory host. Then, the computing device can mark in the page table of the computing device that the page stored in the second memory host is present. Subsequently, the computing device can discard the page stored on the first memory host.

Migrating virtual machines in cluster memory systems

Disclosed are various embodiments for optimized memory tiering. An ideal tier size for a first memory and an ideal tier size for a second memory can be determined for a process. Then, a host computing device can be identified that can accommodate the ideal tier size for the first memory and the second memory. Subsequently, the process can be assigned to the host computing device.

Optimized memory tiering

Disclosed are various approaches for decreasing the latency involved in reading pages from swap devices. These approaches can include setting a first queue in the plurality of queues as a highest priority queue and a second queue in the plurality of queues as a low priority queue. Then, an input/output (I/O) request for an address in memory can be received. The type of the I/O request can be determined, and then the I/O request can be assigned to the first queue or the second queue of the swap device based at least in part on the type of the I/O request.

Low latency virtual memory management

While an application or a virtual machine (VM) is running, a device tracks accesses to cache lines to detect access patterns that indicate security attacks, such as cache-based side channel attacks or row hammer attacks. To enable the device to detect accesses to cache lines, the device is connected to processors via a coherence interconnect, and the application/VM data is stored in a local memory of the device. The device collects the cache lines of the application/VM data that are accessed while the application/VM is running into a buffer and the buffer is analyzed for access patterns that indicate security attacks.

Coherence-based attack detection

Disclosed are various embodiments for improving resiliency and performance of clustered memory. A computing device can acquire a chunk of byte-addressable memory from a cluster memory host. The computing device can then identify an active set of allocated memory pages and an inactive set of allocated memory pages for a process executing on the computing device. Next, the computing device can store the active set of allocated memory pages for the process in the memory of the computing device. Finally, the computing device can store the inactive set of allocated memory pages for the process in the chunk of byte-addressable memory of the cluster memory host.

Resiliency and performance for cluster memory

Disclosed are various embodiments for improving the resiliency and performance for clustered memory. A computing device can mark a page of the memory as being reclaimed. The computing device can then set the page of the memory as read-only. Next, the computing device can submit a write request for the contents of the page to individual ones of a plurality of memory hosts. Subsequently, the computing device can receive individual confirmations of a successful write of the page from the individual ones of the plurality of memory hosts. Then, the computing device can mark the page as free in response to receipt of the individual confirmations of the successful write from the individual ones of the plurality of memory hosts.

A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.

Smart prefetching for remote memory

A device tracks accesses to pages of code executed by processors and modifies a portion of the code without terminating the execution of the code. The device is connected to the processors via a coherence interconnect and a local memory of the device stores the code pages. As a result, any requests to access cache lines of the code pages made by the processors will be placed on the coherence interconnect, and the device is able to track any cache-line accesses of the code pages by monitoring the coherence interconnect. In response to a request to read a cache line having a particular address, a modified code portion is returned in place of the code portion stored in the code pages.

Coherence-based dynamic code rewriting, tracing and code coverage

A device is connected via a coherence interconnect to a CPU with a cache. The device monitors cache coherence events via the coherence interconnect, where the cache coherence events relate to the cache of the CPU. The device also includes a buffer that can contain representations, such as addresses, of cache lines. If a coherence event occurs on the coherence interconnect indicating that a cache line in the CPU's cache is dirty, then the device is configured to add an entry to the buffer to record the dirty cache line.

Using cache coherent FPGAS to track dirty cache lines

Disclosed are various embodiments for improving the resiliency and performance of clustered memory. A computing device can generate at least one parity page from at least a first local page and a second local page. The computing device can then submit a first write request for the first local page to a first one of a plurality of memory hosts. The computing device can also submit a second write request for the second local page to a second one of the plurality of memory hosts. Additionally, the computing device can submit a third write request for the parity page to a third one of the plurality of memory hosts.

The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.

Method and system for tracking state of cache lines

In one set of embodiments, a hardware module of a computer system can receive a stream of addresses corresponding to memory units being accessed by a central processing unit (CPU) of the computer system. The hardware module can further generate a frequency estimate for each address in the stream of addresses, the frequency estimate being indicative of a number of times a memory unit identified by the address has been accessed by the CPU, and can determine, based on the generated frequency estimates, a set of n most frequently accessed memory units.

Techinques for tracking frequently accessed memory

In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.

Low latency host processor to coherent device interaction

Techniques for implementing high availability for persistent memory are provided. In one embodiment, a first computer system can detect an alternating current (AC) power loss/cycle event and, in response to the event, can save data in a persistent memory of the first computer system to a memory or storage device that is remote from the first computer system and is accessible by a second computer system. The first computer system can then generate a signal for the second computer system subsequently to initiating or completing the save process, thereby allowing the second computer system to restore the saved data from the memory or storage device into its own persistent memory.

High availability for persistent memory

Growing community of inventors

Saratoga, CA, United States of America

Pratap Subrahmanyam