Stmicroelectronics International N.v.

Stmicroelectronics S.a.

Stmicroelectronics Pvt. Ltd.

Stmicroelectronics S.r.l.

St-ericsson Sa

Stmicroelectronics (canada), Inc.

Pratap Narayan Singh

Chandrajit Debnath

Ashish Kumar

Rakesh Malik

Stéphane Le Tual

Ankur Bal

Nitin Bansal

Jean-Pierre Blanc

Prashant Singh

Anil Kumar

Vivek Tripathi

Mounir Boulemnakher

Mohit Singh

Arnold James D'Souza

Ashish Kumar Sharma

Shiva Sharath Babu Kaleru

Oleksiy Zabroda

Nicola Vannucci

A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.

Supply voltage compensation for an input/output driver circuit using clock signal frequency comparison

An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.

Circuit and method for generating reference signals for hybrid analog-to-digital convertors

A localized substrate heater is configured to apply variable substrate heating to an integrated bipolar transistor. The base-to-emitter voltage (Vbe) of that bipolar transistor at varying substrate temperature settings is sensed, with the sensed Vbe processed to determine temperature coefficients of the bipolar transistor. The bipolar transistor may, for example, be a circuit component of an integrated temperature sensing circuit.

Temperature sensing circuit with temperature coefficient estimation and compensation using time variable substrate heating

Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

Current steering digital to analog converter with decoder free quad switching

A reference voltage generation circuit, including a first current source in series with a first bipolar transistor; a second current source in series with a first resistor; a third current source in series with a second bipolar transistor, the third current source being assembled as a current mirror with the first current source; a second resistor between the base of the second bipolar transistor and the junction point between the current source and the first resistor; and a fourth current source in series with a third resistor, the junction point between the fourth current source and the third resistor defining a reference voltage terminal.

Reference voltage generation circuit

A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages, to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

Variable delay element

A digital-to-analog converter has an output. An analog-to-digital converter senses a voltage at the output of the digital-to-analog converter and generates a digital voltage signal. A source mismatch estimator processes the digital voltage signal to output an error signal indicative of current source mismatch within the digital-to-analog converter. An error code generator generates a digital calibration signal from the error signal. The digital calibration signal is converted by a redundancy digital-to-analog converter to an analog compensation signal for application to the output of analog-to-digital converter to nullify effects of the current source mismatch.

Self-calibrated digital-to-analog converter

An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

Adaptive delay based asynchronous successive approximation analog-to-digital converter

The invention concerns a circuit comprising: a first circuit block () adapted to receive a first clock signal (CLK) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block () adapted to receive a second clock signal (CLK) and to provide a second output data signal at a time determined by said second clock signal; a clock bus () coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit () coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.

Data synchronization circuit

An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

The invention concerns a circuit comprising: a first transistor () having a first main current node coupled to a first voltage signal (CN), a control node coupled to a second voltage signal (CP) and a second main current node coupled to an output node () of the circuit; a second transistor () having a first main current node coupled to a third voltage signal (CN), a control node coupled to a fourth voltage signal (CP) and a second main current node coupled to said output node of the circuit; and circuitry () adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

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Chahania Chandauli, India

Pratap Narayan Singh