Advanced Micro Devices Corporation

Indian Institute of Science

Department of Electronics and Information Technology

Indian Institute of Science Bangalore

Pratap Kumar Das

Bharadwaj Amrutur

Partha Pratim Ghosh

Prasanth M

A system and method for creating layout for standard cells are described. In various implementations, a semiconductor fabrication process (or process) forms a power signal route in a same metal zero track reserved for power rails. The process forms a contact layer with inserted spacing underneath the power signal route. Along the track, this contact layer has physical contact with the power signal route with a first distance greater than a width of any signal route in any metal layer orthogonal to the power signal route, and has no physical contact with the power signal route with a second distance greater than the width. One or more signal routes in the local interconnect layer are routed through this spacing. Without this spacing, signals would be routed through this area using the metal one layer, which increases signal congestion.

Low congestion standard cells

A system and method for creating layout for standard cells are described. In various implementations, a floating metal net in the metal zero layer of a standard cell is selected for conversion to a power rail. The metal zero layer is a lowest metal layer above the gate region of a transistor. A semiconductor process (or process) forms a power rail in a metal zero track reserved for power rails. The process forms another power rail in a metal zero track reserved for floating metal nets, and electrically shorts the two power rails using a local interconnect layer between the two power rails. The charging and discharging times of a source region physically connected to the two power rails decreases.

Techniques to create power connections from floating nets in standard cells

Embodiments of the disclosure relate to an all-digital technique for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A sub-sampling technique based delay measurement unit capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. A significant improvement in accuracy is obtained for a commercial programmable delay generator chip. The time-precision trade-off feature of the delay measurement unit is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter.

System to generate a predetermined fractional period time delay

A technique for a delay measurement system to measure the skews in a clock distribution network is presented. It uses the principle of sub-sampling to measure and amplify small clock skews and determine an estimate of clock skew by further manipulation if these sampled measurements. The technique can be applied to measure clock skew on a computer chip, between bit-line of a communication bus, or between elements connected by an electronic or optical interconnect.

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Bengaluru, India

Pratap Kumar Das