International Business Machines Corporation

Globalfoundries Inc.

Pratap Chandra Pattnaik

Kattamuri Ekanadham

Joefon Jann

Hubertus Franke

Jose Eduardo Moreira

Manoj N Kumar

Ramanjaneya Sarma Burugula

Chung-Sheng Li

Matt Richard Hogstrom

Nagui Halim

Brad L Brech

Michael D Williams

Hao Yu

Scott W Crowder

Radha P Ratnaparkhi

Mauricio J Serrano

Niteesh Kumar Dubey

Jessica Hui-Chun Tseng

Jessica Tseng

Josyula R Rao

Ilie G Tanase

William Pettit Horn

Yurij Andrij Baransky

Gianfranco Bilardi

Dimitrios Pendarakis

David Bruce Lindquist

Jeffrey Alan Frey

Ravi Shankar

Balachandar Rajaraman

Rodney A Smith

Stefan Pappe

Clifford A Pickover

Harold Wade Cain, Iii

Bruce Gerard Mealey

Rama Krishna Govindaraju

Mandayam Thondanur Raghunath

Thomas Stanley Mathews

Kaoutar El Maghraoui

Il Park

Robert Michael Straub

Beng-Hong Lim

Derek E Williams

Hung Qui Le

Brian William Thompto

Maged M Michael

Mark Edwin Giampapa

Douglas James Joseph

Marc Snir

Rick A Hamilton, Ii

Dung Q Nguyen

Renato John Recio

Bulent Abali

Dennis Merton Newns

Robert William Wisniewski

Yu-Cheng Hsu

David R Safford

Orran Yaakov Krieger

Youssef Drissi

Jong-Deok Choi

Colin George Harrison

Dilip Dinkar Kandlur

Saurabh Desai

Murali Vaddagiri

Sandra Johnson Baylor

Jack Lawrence Kouloheris

Wilm Ernst Donath

Il Mok Park

Simone Sbaraglia

Sandhya Koteshwara

Manoj Kumar

Luiz A DeRose

A data ordering device includes a plurality of inputs N and a plurality of outputs M. There is a sorting network coupled between the plurality of inputs N and the plurality of outputs M. There are one or more latches comprising a buffer coupled between each input of the plurality of inputs N and a corresponding input of the sorting network. There are one or more latches comprising a buffer coupled between each output of the plurality of outputs M and a corresponding output of the sorting network. There is an input for a control signal operative to initiate a sorting of data between the plurality of inputs N and the plurality of outputs M. The data ordering device is coupled to a core of a central processing unit.

Reformatting matrices to improve computing efficiency

Aspects of the present disclosure relate to encrypted data processing (EDAP). Encrypted data from a cache to be loaded into a register file can be accessed. The encrypted data can be decrypted to receive cleartext data. The cleartext data can be written to the register file. The cleartext data can be processed using at least one functional unit to receive cleartext computation results. The cleartext computation results can then be written back to the register file.

Encrypted data processing design including cleartext register files

A system may determine that two instructions may be combined based on a processing power of the processor and a size of the instructions, fuse the two instructions into a pair, map the two instructions with a single register tag, write the register tag into a mapper with bits indicating that the register tag is for a first instruction of the two instructions, write the register tag into the mapper with bits indicating that the register tag is for a second instruction of the two instructions, write the fused instruction pair into an issue queue, issue the fused instruction pair to a vector-scalar transformation units (VSU), and execute the two instructions.

Loosely-coupled slice target file data

Aspects of the present disclosure relate to encrypted data processing (EDAP). A processor includes a register file configured to store ciphertext data, an instruction fetch and decode unit configured to fetch and decode instructions, and a functional unit configured to process the stored ciphertext data. The functional unit further includes a decryption module configured to decrypt ciphertext data from the register file to receive cleartext data using an encryption key stored within the functional unit. The functional unit further includes a local buffer configured to store the cleartext data. The functional unit further includes an arithmetic logical unit configured to generate cleartext computation results using the cleartext data The functional unit further includes an encryption module configured to encrypt the cleartext computation results to generate ciphertext computation results for storage back into the register file.

Encrypted data processing design including local buffers

Embodiments for providing memory access operations for graph analytics by a processor are disclosed. An entire chunk of load and store instructions may be atomically and concurrently executed, where the entire chunk of the load and store instructions are delineated from a plurality of alternative load and store instructions.

Memory access operations for large graph analytics

A Reduced Instruction Set Computer ('RISC') supporting large-word operations in a computing environment is disclosed. In one implementation, in response to receiving one or more control signals from a central processing unit ('CPU'), a set of operations are executed on a state of a special purpose execution unit (&#x201c;SPU&#x201d;) having a plurality of SPU registers, the SPU being associated with the CPU and the state of the SPU having word widths of one or more of the plurality of registers being greater in size than word widths of a plurality of CPU registers of a computing system and a set of state-master bits to synchronize the state of the SPU and a state of the CPU. The results of the set of operations are stored in the plurality of CPU registers or an alternative set of the plurality of SPU registers.

Supporting large-word operations in a reduced instruction set computer ('RISC') processor

Method and systems for creating a sequence of fused instructions. An instruction stream is obtained, and a window of instructions from the instruction stream is examined and one or more groups of instructions that satisfy one or more fusion rules are identified. One or more of the groups of instructions that satisfy the one or more fusion rules are fused and a maximal length data dependence chain in the instruction stream is analyzed by analyzing every node in a dependence graph in a selected window of instructions. Fusion of an instruction group is prevented based on the maximal length data dependence chain.

Instruction fusion using dependence analysis

A method and system are provided. The method includes generating, by a machine-based sentiment prediction generator, respective machine-determined sentiment predictions for each of a plurality of software patches using sentiment analysis. The method further includes setting, by a sentiment-based confidence value generator, a confidence value for each of the plurality of software patches based on the machine-determined sentiment predictions. The method also includes at least one of selecting and prioritizing, by a software patch selector and prioritizer, at least one of the plurality of software patches based on the respective confidence value therefor.

Software patch management incorporating sentiment analysis

A processor can scan a portion of a vector to identify first nonzero entries. The processor can scan another portion of the vector to identify second nonzero entries. The processor can scale a portion of a matrix using the first nonzero entries to generate first intermediate elements. The processor can scale another portion of the matrix using the second nonzero entries to generate second intermediate elements. The processor can store the first intermediate elements in a first buffer and store the second intermediate elements in a second buffer. The processor can copy a subset of the first intermediate elements from the first buffer to a memory and copy a subset of the second intermediate elements from the second buffer to the memory. The subsets of first and second intermediate elements can be aggregated to generate an output vector.

Dual phase matrix-vector multiplication system

An instruction fusion system in which instructions are tagged with extra bits to specify the conditions by which the instructions can be fused is provided. A computing device receives a first instruction to be executed at a processor. The computing device receives a first fusion tag that corresponds to the first instruction, the first fusion tag specifying a condition for fusing the first instruction with another instruction. The computing device determines whether the first instruction is allowed to fuse with a second instruction based on the first fusion tag. When the first instruction is allowed to fuse with the second instruction, the computing device generates a fused instruction based on the first instruction and the second instruction. The computing device executes the fused instruction at the processor.

Mechanism for instruction fusion using tags

A computing system includes a plurality of functional units, each functional unit having one or more inputs and an output. There is a shared memory block coupled to the inputs and outputs of the plurality of functional units. There is a private memory block assigned to each of the plurality of functional units. An inter functional unit data bypass (IFUDB) block is coupled to the plurality of functional units. The IFUDB is configured to route signals between the one or more functional units without use of the shared memory block.

Processor core design optimized for machine learning applications

Embodiments include methods, computing systems and computer program products for identifying and tracking frequently accessed registers in a processor of a computing system. Aspects include: creating a list of top accessed registers of certain registers in processor, each register having a corresponding register usage counter, initializing each register usage counter, starting a register usage monitoring mode, examining each register usage counter, and updating list of top accessed registers, stopping register usage monitoring mode, and updating a register file partition assignment when the list of top accessed registers is identified. Once the list of top accessed registers is identified, stopping the programs and bring its threads of execution to quiescent, moving registers between register file partitions until all registers on the list of top accessed registers are in the fully-ported register file partition, and resuming executions of the program and its threads.

Identifying and tracking frequently accessed registers in a processor

A processor core and methods for managing the processor core. The processor core comprises of a plurality of lanes, each lane comprising a copy of a register file logically shared across the plurality lanes and a plurality of functional units, at least two of the functional units sharing a common cache and a common control unit, where the common control unit concurrently dispatches multiple consecutive instances of an instruction corresponding to multiple successive instances of an inner loop to the plurality of functional units of at least a proper subset of the plurality of lanes; and one or more registers of each copy of the register file, each register being configurable to write a data result from at least one of the functional units to a register in a lane-local mode, a lane-forward mode, and a normal mode.

Efficient performance of inner loops on a multi-lane processor

Various embodiments execute a program with improved cache efficiency. In one embodiment, a first subset of operations of a program is performed on a plurality of objects stored in one or more data structures. The first subset of operations has a regular memory access pattern. After each operation in the first subset of operations has been performed, results of the operation are stored in one of the plurality of queues. Each queue in the plurality of queues is associated with a different cacheable region of a memory. A second subset of operations in the program is performed utilizing at least one queue in the plurality of queues. The second subset of operations utilizes results of the operations in the first subset of operations stored in the queue. The second subset of operations has an irregular memory access pattern that is regularized by localizing memory locations accessed by the second subset of operations to the cacheable region of memory associated with the at least one queue. Results of each operation performed in the second subset of operations are stored in memory.

Reducing memory access latency in scatter/gather operations

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Ossining, NY, United States of America

Pratap Chandra Pattnaik