Intel Corporation

Prasoonkumar Surti

Abhishek R Appu

Joydeep Ray

Altug Koker

Balaji Vembu

Vasanth Ranganathan

Subramaniam M Maiyuran

Karthik Vaidyanathan

Kamal Sinha

Travis T Schluessler

Elmoustapha Ould-Ahmed-Vall

Murali Ramadoss

Michael Apodaca

Kiran Chand Veernapu

Adam T Lake

John H Feit

Nikos Kaburlasos

Linda L Hurd

Ben J Ashbaugh

Abhishek Venkatesh

Chandrasekaran Sakthivel

Wenyin Fu

Jonathan Kennedy

Scott R Janus

Justin E Gottschlich

David M Puffer

Lakshminarayanan Striramassarma

Nicolas C Galoppo Von Borries

Atsuo Kuwahara

Hugues Labbe

Varghese George

Guei-Yuan Lueh

Ankur N Shah

Sara S Baghsorkhi

Jeffery S Boles

Feng Chen

Dukhwan Kim

Narayan Srinivasa

Aravindh V Anantaraman

Jacek Kwiatkowski

Carsten Benthin

Mike MacPherson

Bhushan M Borole

Kai Xiao

Devan Burke

Gabor Liktor

Rajkishore Barik

Farshad Akhbari

Valentin Andrei

Sanjeev S Jahagirdar

Nadathur Rajagopalan Satish

Jill MacDonald Boyce

John Charles Weast

Eriko Nurvitadhi

Pattabhiraman K

Stanley J Baran

Tsung-Han Lin

Gokcen Cilingir

Deepak Shashidhar Vembar

Josh B Mastronarde

Narayan Biswal

James M Holland

Sven Woop

Tomas G Akenine-Moller

Peter L Doyle

Ingo Wald

James A Valerio

Niranjan L Cooray

Mike B Macpherson

Liwei Ma

Tomer Bar-On

Selvakumar Panneer

John G Gierach

Thomas A Piazza

Christopher J Hughes

Carl S Marshall

Aditya Navale

Carl Jacob Munkberg

Karthik Veeramani

Rajesh Poornachandran

Lidong Xu

Jon N Hasselgren

Xiaoming Chen

Hong Jiang

Kun Tian

Jason Daniel Tanner

Vallabhajosyula S Somayazulu

Daniel Pohl

Larry D Seiler

Michael S Strickland

Glen J Anderson

Yi-Jen Chiu

Eric C Samson

Robert M Toth

Zhi Hu Wang

Alexander F Heinecke

Anbang Yao

Zhi Jun Wang

Dan Baum

Robert S Chappell

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Dynamic memory reconfiguration

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

Systolic arithmetic on sparse data

Methods, systems and apparatuses may provide for technology that identifies that a first thread group of a pixel location is associated with a first shading rate, identifies that a second thread group of the pixel location is associated with a second shading rate, wherein the first shading rate is different from the second shading rate. The technology marks a dependency of the first thread group on the second thread group.

Dynamic dependency scoreboard for overlapping pixels of primitives

Apparatus and method for stable and short latency sorting. For example, one embodiment of a processor comprises: an input circuit to receive a set of N input values to be sorted into a sorted order; comparison circuitry to compare each input value with all other input values in parallel to generate at least N*(N−1)/2 comparison result values; matrix generation circuitry and/or logic to generate a result matrix having a row associated with each input value, a plurality of bits in each row comprising comparison result values indicating results of comparisons with other input values, wherein a first region of the result matrix is to store a first set of bits comprising the N*(N−1)/2 comparison result values and a second region of the result matrix, opposite the first region, is to store a second set of bits comprising an inverse of the N*(N−1)/2 comparison result values; a parallel adder circuit to perform parallel additions of the bits in each row to generate N unique result values; and sorting circuitry to index into the N unique result values to return the sorted order.

Apparatus and method for performing a stable and short latency sorting operation

An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determine that a set of memory requests in the stream of instructions access a same memory page; and set a marker in a first request of the set of memory requests; and arbitration circuitry communicably coupled to the L1 cache, the arbitration circuitry to route the set of memory requests to memory comprising the memory page and to, in response to receiving the first request with the marker set, remain with the processing resource to process the set of memory requests.

Efficient data sharing for graphics data processing operations

Interleaving of variable bitrate streams for GPU implementations is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a super-compression encoder pipeline to provide variable width interleaved coding; and memory for storage of data, wherein the graphics processor is to perform parallel dictionary encoding on a bitstream of symbols one of multiple workgroups, the workgroup to employ a plurality of encoders to generate a plurality of token-streams of variable lengths; create a histogram including at least tokens from the plurality of token-streams for the workgroup to generate an optimized entropy code; entropy code each of the plurality of token-streams for the workgroup into an encoded bitstream; and variably interleave the encoded bitstreams to generate an interleaved bitstream and bookkeep a size of the interleaved bitstream.

Interleaving of variable bitrate streams for GPU implementations

Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.

Sparse optimizations for a matrix accelerator architecture

Methods, systems and apparatuses provide for graphics processor technology that routes untyped unordered access view (UAV) messages to a next level memory cache, routes typed UAV messages and render target messages to a pixel pipeline, and processes, via the pixel pipeline, the typed UAV messages. The technology can also provide for the pixel pipeline to perform a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource, calculate a memory address for each pixel associated with the typed UAV message, and collect a plurality of fragments from processed typed UAV messages.

Typed unordered access view overloading on pixel pipeline

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.

Graphics system with additional context

Methods, systems and apparatuses may provide for technology that determines that a state of a plurality of primitives is associated with out-of-order execution. The plurality of primitives is associated with a raster order. The technology reorders the plurality of primitives from a raster order, and distributes one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of a graphics processor or a graphics pipeline of the graphics processor.

Out-of-order pixel shading and rasterization

A graphics processing apparatus includes graphics processors connected by a network connection, where the graphics processors pass compressed data. A first graphics processor stores data blocks as compressed data in a memory. The compressed data has data blocks of variable size, where a size of a block of compressed data depends on a compression ratio of the block of compressed data. A second graphics processor also stores data blocks as compressed data. The first graphics processor concatenates a variable number of blocks of compressed data into a packet of fixed size to send to the second graphics processor. The packet has a variable number of blocks of compressed data depending on the compression ratios of the multiple blocks of compressed data.

Scale up and out compression

Apparatuses including general-purpose graphics processing units having on chip dense memory for temporal buffering are disclosed. In one embodiment, a graphics multiprocessor includes a plurality of compute engines to perform first computations to generate a first set of data, cache for storing data, and a high density memory that is integrated on chip with the plurality of compute engines and the cache. The high density memory to receive the first set of data, to temporarily store the first set of data, and to provide the first set of data to the cache during a first time period that is prior to a second time period when the plurality of compute engines will use the first set of data for second computations.

On chip dense memory for temporal buffering

Methods, systems and apparatuses may provide for technology that identifies first graphics data that is associated with spatially proximate positions. The technology identifies second graphics data that is associated with spatially proximate positions, and interleaves the first and the second graphics data across a plurality of storage tiles.

Compression and interleaving of spatially proximate data

Growing community of inventors

Folsom, CA, United States of America

Prasoonkumar Surti