Intel Corporation

Prasoonkumar Surti

Abhishek R Appu

Joydeep Ray

Altug Koker

Balaji Vembu

Vasanth Ranganathan

Karthik Vaidyanathan

Subramaniam M Maiyuran

Kamal Sinha

Travis T Schluessler

Elmoustapha Ould-Ahmed-Vall

Murali Ramadoss

Michael Apodaca

Kiran Chand Veernapu

Adam T Lake

John H Feit

Linda L Hurd

Nikos Kaburlasos

Ben J Ashbaugh

Chandrasekaran Sakthivel

Abhishek Venkatesh

Justin E Gottschlich

David M Puffer

Wenyin Fu

Jonathan Kennedy

Scott R Janus

Atsuo Kuwahara

Lakshminarayanan Striramassarma

Nicolas C Galoppo Von Borries

Hugues Labbe

Ankur N Shah

Sara S Baghsorkhi

Jeffery S Boles

Varghese George

Guei-Yuan Lueh

Feng Chen

Dukhwan Kim

Narayan Srinivasa

Aravindh V Anantaraman

Jacek Kwiatkowski

Carsten Benthin

Mike MacPherson

Bhushan M Borole

Kai Xiao

Devan Burke

Gabor Liktor

Sanjeev S Jahagirdar

John Charles Weast

Rajkishore Barik

Farshad Akhbari

Jill MacDonald Boyce

Nadathur Rajagopalan Satish

Eriko Nurvitadhi

Stanley J Baran

Pattabhiraman K

Gokcen Cilingir

Tsung-Han Lin

Philip R Laws

Narayan Biswal

Deepak Shashidhar Vembar

Josh B Mastronarde

Sven Woop

Nilesh V Shah

James M Holland

Tomas G Akenine-Moller

James A Valerio

Liwei Ma

Mike B Macpherson

Peter L Doyle

Ingo Wald

Niranjan L Cooray

Tomer Bar-On

Aditya Navale

Selvakumar Panneer

John G Gierach

Thomas A Piazza

Christopher J Hughes

Carl S Marshall

Carl Jacob Munkberg

Karthik Veeramani

Rajesh Poornachandran

Lidong Xu

Jon N Hasselgren

Xiaoming Chen

Yi-Jen Chiu

Hong Jiang

Kun Tian

Jason Daniel Tanner

Vallabhajosyula S Somayazulu

Daniel Pohl

Larry D Seiler

Michael S Strickland

Glen J Anderson

Eric C Samson

Robert M Toth

Zhi Hu Wang

Anbang Yao

Alexander F Heinecke

Zhi Jun Wang

Dan Baum

Apparatus and method for scheduling inference tasks. For example, one embodiment of an apparatus comprises: a plurality of compute units (CUs) to execute inferencing routines, an inferencing routine comprising a plurality of phases, at least one CU comprising execution circuitry configurable to operate in a single instruction multiple data (SIMD) mode or a single instruction multiple thread (SIMT) mode; and dispatching hardware logic to determine whether a current phase of an inferencing routine is to be executed in the SIMD mode or the SIMT mode, and to dispatch instructions of the current phase for execution by the execution circuitry of a CU in accordance with the SIMD mode or the SIMT mode, respectively.

Apparatus and method for scheduling inference tasks

Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

Multi-render partitioning

One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.

Immediate offset of load store and atomic instructions

A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.

Unified stateless compression system for universally consumable compression

A mechanism is described for detecting, at training time, information related to one or more tasks to be performed by the one or more processors according to a training dataset for a neural network, analyzing the information to determine one or more portions of hardware of a processor of the one or more processors that is configurable to support the one or more tasks, configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks, and monitoring utilization of the hardware via a hardware unit of the graphics processor and, via a scheduler of the graphics processor, adjusting allocation of the one or more tasks to the one or more portions of the hardware based on the utilization.

Coordination and increased utilization of graphics processors during inference

For example, one embodiment of an apparatus comprises: ray traversal hardware logic to perform traversal operations to traverse rays through a bounding volume hierarchy (BVH) comprising a plurality of BVH nodes, the ray traversal hardware logic comprising a plurality of traversal storage banks to store traversal data associated with the BVH nodes and/or the rays as the ray traversal hardware logic performs the traversal operations; and a cache comprising a plurality of cache banks to store the traversal data prior to being moved into the traversal storage banks for processing by the ray traversal hardware logic; and an inter-bank interconnect comprising: a point-to-point switch matrix to couple any of the cache banks to any of the traversal storage banks; an arbiter/allocator to control the point-to-point switch matrix to establish a particular group of interconnections between the cache banks and the traversal storage banks in a given clock cycle.

Apparatus and method for routing data from ray tracing cache banks

Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.

Compression for sparse data structures utilizing mode search approximation

An apparatus to facilitate a dynamically scalable and partitioned copy engine is disclosed. The apparatus includes a processor comprising copy engine hardware circuitry to facilitate copying surface data in memory and comprising: a plurality of copy front-end hardware circuitry to generate a plurality of surface data sub-blocks, wherein a number of the plurality of copy front-end hardware circuitry corresponds to a number of partitions configured for the processor, with each partition associated with a single copy front-end hardware circuitry; a plurality of copy back-end hardware circuitry to operate in parallel to process the plurality of surface data sub-blocks to perform memory accesses, wherein subsets of the plurality of copy back-end hardware circuitry are each associated with the single copy front-end hardware circuitry associated with each partition; and a connectivity matrix hardware circuitry to communicably connect the plurality of copy front-end hardware circuitry to the plurality of copy back-end hardware circuitry.

Dynamically scalable and partitioned copy engine

Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.

Lossless compression for multisample render targets alongside fragment compression

An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.

Virtual reality apparatus and method including prioritized pixel shader operations, alternate eye rendering, and/or augmented timewarp

Examples described herein relate to a manner of determining a number of bits to encode compression data. Some examples include: compressing pixel data of a region of pixels in a frame; determining a number of bits associated with at least two partitions; utilizing the determined number of bits to encode residual values generated from the compressing the pixel data; and storing the encoded residual values. In some examples, the at least two partitions comprise a first partition and a second partition. Some examples include: encoding residuals in the first partition using a number of bits associated with the first partition and encoding residuals in the second partition using a number of bits associated with the second partition. Some examples include: determining a distribution of bins of residuals, wherein each different bin represents a number of bits used to encode a residual value and determining a midpoint of a total number of residuals as a bin that stores a residual that is approximately 50 percentile of the total number of residuals of the distribution.

Memory allocation technologies for data compression and de-compression

A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

Adaptive resolution of point cloud and viewpoint prediction for video streaming in computing environments

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Dynamic memory reconfiguration

Growing community of inventors

Folsom, CA, United States of America

Prasoonkumar Surti