Intel Corporation

Prashanth R Gadila

Nabajit Deka

Asad Azam

Riccardo Mariani

Alessandro Campinoti

Giuseppe Capodanno

Roger May

Elisa Spano

Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.

Single chip multi-die architecture having safety-compliant cross-monitoring capability

Techniques are disclosed for combining diagnostic features at different levels (with a special consideration of the application-oriented measures) though a quantitative analysis that provides evidence supporting a claimed diagnostic coverage (DC) calculation for circuits to meet defined functional safety standards. These techniques implement a parametrized approach to allow tuning by a system integrator according to its specific software application environment. The required safety level or DC goals may thus be attained based upon the results of the safety analysis (and failure rates) provided by a device manufacturer.

Quantitative analysis and diagnostic coverage (DC) calculation of application-oriented safety measures in complex systems

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Hyderabad Telangana, India

Prashanth R Gadila