Other

Intel Corporation

Prashanth Nimmala

Robert J Greiner

Lily Pao Looi

Rupin H Vakharwala

Aimee D Wood

Jeff Van Tran

Hamid-Reza S Bonakdar

Marcus W Song

James A Beavens

An apparatus and method is described herein for providing instantaneous, efficient cache state recover upon an end of speculative execution. Speculatively accessed entries of a cache memory are marked as speculative, which may be on a thread specific basis. Upon an end of speculation, the speculatively marked entries are transitioned in parallel by a speculative port to their appropriate, thread specific, non-speculative coherency state; these parallel transitions allow for instantaneous commit or recovery of speculative memory state.

Apparatus, method, and system for instantaneous cache state recovery from speculative abort/commit

In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.

Integrating intellectual property (IP) blocks into a processor

Growing community of inventors

Beaverton, OR, United States of America

Prashanth Nimmala