Intel Corporation

Prashanth Kalluraya

Bruce L Fleming

Joydeep Ray

Mahesh U Wagh

Shreekant S Thakkar

Uttam K Sengupta

Sridhar Lakshmanamurthy

Kenneth D Shoemaker

Rajasekaran Andiappan

Suketu R Partiwala

Sami Yehia

An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power.

Ultra low power architecture to support always on path to memory

Methods and apparatus relating to increasing energy efficiency of sensor controllers are described. In an embodiment, logic (e.g., within a sensor controller) performs one or more tasks corresponding to acquisition of data from one or more sensors. The logic performs the one or more tasks to allow a processor core of the sensor controller to enter (or stay in) a low power consumption state during performance of the one or more data acquisition tasks. Other embodiments are also disclosed and claimed.

Techniques for increasing energy efficiency of sensor controllers that receive data from one or more sensors

In an embodiment, an apparatus includes a consuming logic to request and process data including a critical data portion and a second data portion, the data stored in a memory coupled to a processor interposed between the apparatus and the memory. In addition, the apparatus includes a protocol stack logic coupled to the consuming logic to issue a read request to the memory via the processor to request the data and to receive a plurality of completions responsive to the read request. In an embodiment, the protocol stack logic includes a completion handling logic to send data of a first of the completions to the consuming logic before protocol stack processing is completed on the completions. Other embodiments are described and claimed.

Reducing latency of unified memory transactions

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Foster City, CA, United States of America

Prashanth Kalluraya