Freescale Semiconductor,inc.

Samsung Electronics Co., Ltd.

Motorola Corporation

Prashant U Kenkare

Ravindraraj Ramaraju

Shayan Zhang

Andrew Christopher Russell

Troy L Cooper

David R Bearden

James R Pfiester

James David Burnett

Matthew S Berzins

Jogendra C Sarker

Ambica Ashok

Perry H Pelley

Michael D Snyder

George P Hoekstra

Jack M Higman

Sumeer Goel

Jeremiah T C Palmer

Jin Seung Son

Cody B Croxton

William C Moyer

Bich-Yen Nguyen

Min-Su Kim

Alexander Hoefler

Bradford Lawrence Hunter

Frank P Helms

Kent J Cooper

Shih-Wei Sun

Maciej Bajkowski

Brian M Millar

Hema Ramamurthy

Jeffrey William Waldrip

David Burnett

Peter M Ippolito

Jan-Michael Huber

Michael Zimin

Kenneth Hicks

Gary A Mussemann

Sunitha Manickavasakam

Mihir S Sabnis

Ravindraj Ramaraju

Karen Delk

Kevin E Klein

Shahnaz Nagle

Jin-Seung Son

Rajesh Kapaluru

Pelley H Perry

According to one general aspect, an apparatus may include a global bit line, and a plurality of memory banks. The global bit line may be configured to facilitate a memory access. Each memory bank may include a local keeper-precharge circuit coupled between a power supply and the global bit line, and a control circuit configured to control, at least in part, the local keeper-precharge circuit.

Distributed global-bitline keeper/precharge/header circuit for low voltage operation

According to one general aspect, an apparatus may include a power header and a logic circuit. The power header may include a gate terminal, a first channel terminal, a second channel terminal, and a bulk terminal coupled with a first voltage power signal. The power header may be configured to perform one of dynamically coupling or decoupling a logic circuit with the first voltage power signal. The logic circuit may include a bulk terminal coupled with a second voltage power signal and a power terminal that is either dynamically coupled or decoupled, as determined by the power header, with the first voltage power signal. A power sequencing signal may be included in the apparatus and may be configured to control the power header such that, when active, the power header couples the logic circuit with the first voltage power signal after the second voltage power signal is high.

System and method for providing an area efficient and design rule check (DRC) friendly power sequencer for digital circuits

According to one general aspect, an apparatus may include a bit cell configured to store a bit of information. The apparatus may include a first voltage configured to supply the bit cell with power. The apparatus may include a wordline driver configured to cause the bit to be read from the bit cell. The wordline driver may be configured to operate during a read operation at a second voltage that is lower than the first voltage, wherein the second voltage is determined by charge sharing between a plurality of capacitances. The wordline driver may include a switch configured to disconnect the wordline driver from the first voltage before an input word line signal is applied to the wordline driver, and wherein the switch is responsive to a clock signal.

Method and apparatus for read assist to achieve robust static random access memory (SRAM)

According to one general aspect, an apparatus may include a first power supply configured to generate a first power signal having one of a plurality of voltages, and a second power supply configured to generate a second power signal that includes a voltage equal to or higher than a voltage of the first power signal. The apparatus may include a first electrical circuit configured to be powered by the first power supply. The apparatus may also include a power mode controller configured to: determine the voltage of the first power signal during the next power state, and generate a selector control signal based upon the voltage of the first power signal. The apparatus may also include a power supply selector configured to dynamically electrically couple a second electrical circuit with either the first power signal or the second power signal, based upon the selector control signal.

Dual supply memory

A static random access memory includes a memory cell array, a control logic configured to generate a first write clock signal and a second write clock signal each of which having a pulse width shorter than a pulse width of a clock signal in response to the clock signal, a row decoder configured to select a word line in response to the second write clock signal during a write operation, a column selector configured to select a bit line and an inverted bit line, a sense amplifier configured to sense states of the selected bit line and the selected inverted bit line during a read operation and a write driver configured to bias the selected bit line and the selected inverted bit line in response to the first write clock signal during the write operation.

Static random access memory with bitline boost

Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is 'borrowed' from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.

Integrated clock gater (ICG) using clock cascode complimentary switch logic

According to the inventive concepts disclosed herein, a level shifter can include an input node in a first voltage domain and an output node in a second voltage domain, higher than the first voltage domain. The input node receives an input signal in the first, lower-voltage domain, and the output node is configured to output a representation of the input signal in the second, higher-voltage domain. A lower-voltage control circuit can control a supply of the lower-voltage level to a boundary node arranged at a boundary between the first and second domains. A higher-voltage control circuit can also be provided to control a supply of the higher-voltage level to the boundary node. The lower-voltage control circuit can cut off the lower-voltage supply to the boundary node when the higher-voltage control circuit supplies the higher-voltage level to the boundary node. The higher-voltage control circuit can, for instance, include logic circuitry that enables and disables a connection to the higher-voltage supply. Alternatively, the higher-voltage control circuit can include a boost capacitor coupled between the output node and the boundary node.

Voltage level shifter and systems implementing the same

A wordline driver supply block supporting multiple operation modes of a memory of a microprocessor in a device for reducing power consumption thereof.

SRAM wordline driver supply block with multiple modes

A semiconductor circuit includes: a first circuit configured to provide first voltage to an output node when a voltage level of an input node is at a first level; a second circuit configured to provide second voltage to the output node when the voltage level of the input node is at a second level; and a third circuit configured to provide third voltage to the output node when the second voltage is provided to the output node, where the second circuit is turned off when the third voltage is provided to the output node.

Semiconductor circuit

A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.

Flip-flop having shared feedback and method of operation

A method and data processing system for accessing an entry in a memory array by placing a tag memory unit () in parallel with an operand adder circuit () to enable tag lookup and generation of speculative way hit/miss information () directly from the operands () without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands () are applied with a carry-out value (Cout) to a content-addressable memory array () to generate two speculative hit/miss signals. A sum value (EA) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output ().

Memory management unit tag memory

A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.

System and method for memory array access with fast address decoder

Growing community of inventors

Autin, TX, United States of America

Prashant U Kenkare