Stmicroelectronics International N.v.

Prashant Singh

Pratap Narayan Singh

A squelch detection device is provided. The squelch detection device receives first and second input signals and first and second threshold voltages. The squelch detection device determines a first common mode of the first and second input signals and a second common mode of the first and second threshold voltages. The squelch detection device averages the first common mode with the second common mode to produce an average common mode and sets the first common mode of the first and second input signals to the average common mode. The squelch detection device sets the second common mode of the first and second threshold voltages to the average common mode and determines a state of a squelch signal, indicative of whether the first and second input signals are attributable to noise, based on the first and second input signals and the first and second threshold voltages.

Squelch detection device

A circuit has a first window comparator determining whether a signal at a first input has a voltage higher than a first threshold but lower than a second threshold, and a second window comparator determining whether a signal at a second input has a voltage higher than the first threshold but lower than the second threshold. A logic circuit generates pulses in response to either the first window comparator determining that the signal at the first differential input has a voltage higher than the first threshold but lower than the second threshold or the second window comparator determining that the signal at the second input has a voltage higher than the first threshold but lower than the second threshold. A filter circuit receives the pulses from the logic circuit and generates a flag indicating that the signal is invalid, based upon pulses received from the logic circuit.

Circuit for determining whether an actual transmission was received in a low-voltage differential sensing receiver

A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.

Supply voltage compensation for an input/output driver circuit using clock signal frequency comparison

A power supply voltage detector circuit monitors a ramping supply voltage and selectively enables a voltage divider for operation to divide the ramping supply voltage in response to the ramping supply voltage exceeding a first threshold. Additionally, a variable resistance of the voltage divider is changed in response to the ramping supply voltage exceeding a second threshold. A voltage output from the voltage divider is used to generate a bandgap voltage used as a reference voltage in comparison operations for controlling enabling of the voltage divider and selection of the variable resistance.

Stress tolerant power supply voltage detector circuit operable over a wide range of power supply voltages

Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.

Low power general purpose input/output level shifting driver

An integrated circuit includes an IO node, and an IO driver coupled thereto. The IO driver has a first driving circuit with a first PMOS transistor having a source coupled to a supply node and a gate coupled to receive a PMOS driving signal, and a first NMOS transistor having a source coupled to ground, a drain coupled to the drain of the first PMOS transistor, and a gate coupled to receive a NMOS driving signal. The IO driver also has a second driving circuit with a second PMOS transistor having a source coupled to the supply node and a gate coupled to receive a first delayed version of the PMOS driving signal, and a second NMOS transistor having a drain coupled to the drain of the second PMOS transistor, a source coupled to ground, and a gate coupled to receive a first delayed version of the NMOS driving signal.

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Greater Noida, India

Prashant Singh