Integrated Device Technology, Inc.

Prashant Shamarao

Brian Butka

Yonggang Chen

David J Klein

Brad Luis

Alejandro F Gonzalez

Bruce Lorenz Chin

Curt Karnstedt

Paul Joseph Murtagh

Moussa Sobaiti

Jason Zhi-Cheng Mo

Yew-Keong Chong

Robert W Shrank

Mario Montana

XinXin Shao

Yew Keong Chong

Jim K Harris

Jianghui Su

A method and apparatus for a novel adaptive equalization technique for a Serializer/Deserializer receiver is disclosed. In one approach, adjustment of AC and DC gains is performed before DFE coefficients are adjusted. Further after the equalization an electrical idle threshold may be set based on the results of the equalization.

Method and apparatus for novel adaptive equalization technique for serializer/deserializer links

A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.

DRAM interface circuits that support fast deskew calibration and methods of operating same

A method and apparatus for source synchronous testing have been disclosed. In one case a data signal is delayed and a selectively activated delay is applied to a clock. This allows the clock to be positioned before the data and also after the data.

Method and apparatus for source synchronous testing

Multi-queue first-in first-out (FIFO) memory devices include multi-port register files that provide write count and read count flow-through when the write and read queues are equivalent. According to some of these embodiments, a multi-queue FIFO memory device includes a write flag counter register file that is configured to support flow-through of write counter updates to at least one read port of the write flag counter register file. This flow-through occurs when an active write queue and an active read queue within the FIFO memory device are the same. A read flag counter register file is also provided, which supports flow-through of read counter updates to at least one read port of the read flag counter register file when the active write queue and the active read queue are the same.

Multi-queue FIFO memory devices that support flow-through of write and read counter updates using multi-port flag counter register files

A data path includes a downstream stage that strobes data at an input thereof responsive to a first control signal, an upstream stage that sends data to the input of the downstream stage responsive to a second control signal, and a control circuit operative to fix timing of the second control signal to timing of the first control signal. The data path may further include a second upstream stage that sends data to an input of the first upstream stage responsive to a third control signal having a timing with respect to the second control signal that varies responsive to a frequency at which data is transferred along the data path. A fixed delay circuit, e.g., a fixed delay circuit in a forward path of a DLL or PLL, may generate the first control signal from the second control signal.

Data paths with receiver timing fixable to a downstream stage and methods of operation thereof

Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially. The register file may include multiple register subfiles, and the controller may include multiple controller subblocks.

Integrated circuit FIFO memory devices that are divisible into independent FIFO queues, and systems and methods for controlling same

Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively. The second totem pole driver stage has at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively. The linearity of the output driver circuit is enhanced by including a first resistive element that extends between the first and second totem pole driver stages. The first resistive element has a first terminal, which is electrically coupled to drain terminals of the at least one PMOS pull-up transistor and the at least one NMOS pull-down transistor in the first totem pole driver stage, and a second terminal, which is electrically coupled to source terminals of the at least one NMOS pull-up transistor and the at least one PMOS pull-down transistor in the second totem pole driver stage.

Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control

Integrated circuit output buffers include primary and secondary pull-down transistors and an output signal line electrically coupled to a drain of the primary pull-down transistor and a drain of the secondary pull-down transistor. A preferred control circuit is also provided. The control circuit turns on the primary pull-down transistor during first and second consecutive portions of a pull-down time interval and uses a signal fed back from the output signal line to control the timing of when a gate of the secondary pull-down transistor is electrically connected to a drain of the secondary pull-down transistor during the first portion of the pull-down time interval and also control the timing of when the gate electrode of the secondary pull-down transistor is electrically connected to a source of the secondary pull-down transistor during the second portion of the pull-down time interval. A pull-down portion of the control circuit may include a gate pull-up transistor having a drain electrically connected to the drain of the secondary pull-down transistor and a source electrically connected to a gate of the secondary pull-down transistor, and a gate pull-down transistor having a drain electrically connected to the gate of the secondary pull-down transistor and a source electrically connected to a source of the secondary pull-down transistor. These gate pull-up and pull-down transistors can be utilized to selectively turn on the secondary pull-down transistor during a first leading portion of a pull-down time interval and then turn off the secondary pull-down transistor during a second trailing portion of the pull-down time interval.

Integrated circuit output buffers having control circuits therein that utilize output signal feedback to control pull-up and pull-down time intervals

Integrated circuit output buffers include pull-down an pull-up circuits and a control circuit that utilizes a preferred feedback circuit to facilitate a reduction in simultaneous-switching noise during pull-down and pull-up operations and also improve the impedance matching characteristics of the output buffers during DC conditions. The preferred feedback circuit also limits the degree to which external noise can influence operation of the control circuit. Each of the pull-down and pull-up circuits may comprise a respective pair of primary and secondary transistors. The pull-down circuit is preferably configured so that the primary and secondary pull-down transistors (e.g., NMOS transistors) are electrically coupled to an output signal line (through an ESD protection resistor) and a first reference signal line (e.g., Vss). The control circuit is designed to activate the pull-down circuit by turning on both the primary and secondary pull-down transistors during a leading portion of the pull-down time interval and by turning off the secondary pull-down transistor during a trailing portion of the pull-down time interval using a first feedback switch that is electrically coupled in series between the output signal line and a gate electrode of the secondary pull-down transistor so that a signal representing a potential of said output signal line can be passed through the first feedback switch to the gate electrode of the secondary pull-down transistor.

Integrated circuit output buffers having feedback switches therein for reducing simultaneous switching noise and improving impedance matching characteristics

The function selection signal of an ALU is resistively decoupled or serially coupled to the input multiplexers of the ALU. By producing delayed function selection signals and decoupling the delayed function signals from the input multiplexers, the input multiplexers are serially activated. This need not impact the overall speed of the ALUs, since the adders are also serially activated by virtue of the carry signal ripple. However, by resistively decoupling the function selection signal from the input multiplexers, the load seen by the input driver that drives the function selection signal inputs of the multiplexer may be reduced, thereby allowing the least significant bit input multiplexer to be activated more rapidly. Moreover, resistive decoupling may be implemented by polysilicon resistors, thereby allowing metal interconnect layers in the integrated circuit to be used for other purposes.

Resistive decoupling of function selection signals from input

Integrated circuit output buffers include first and second pull-down switches and a preferred pull-down control circuit which utilizes a preferred feedback technique to facilitate a reduction in simultaneous-switching noise during pull-down operations and also improve the impedance matching characteristics of the output buffers during DC conditions. The preferred feedback technique also limits the degree to which external noise can influence operation of the pull-down control circuit. First and second pull-up switches and a pull-up control circuit are also provided to improve simultaneous-switching noise and impedance matching characteristics during pull-up operations in a similar manner. The first and second pulldown switches are electrically connected in parallel between an output of the buffer and a first reference signal line (e.g., Vss) and the first and second pull-up switches are electrically connected in parallel between an output of the buffer and a second reference signal line (e.g., Vdd). The pull-down and pull-up switches may comprise NMOS and PMOS transistors, respectively.

Growing community of inventors

Alpharetta, GA, United States of America

Prashant Shamarao