Synaptics Corporation

Netlogic Microsystems, Inc

Prashant Shamarao

Stephen L Morein

Joseph Kurth Reynolds

Jeffrey Lukanc

Hirokazu Hatayama

Kota Kitamura

Kenji Yamazumi

Robert H Bishop

Ji Park

Xuexin Liu

Shao-Jen Lim

Bradley C Malemezian

Zhibing Liu

Chris DeMarco

Rohit Singhal

Jifeng Liu

Alex Reed

A display driver includes: a receiver configured to receive image data of each line of a display panel from an external device; a line latch circuit having a line latch configured to latch the image data of each line received by the receiver in response to a strobe signal; a driving circuit section which drives the display panel in response to the image data latched by the line latch; and a timing controller configured to generate the strobe signal. The receiver is configured to detect occurrence of transmission error in data transmission about each line. The timing controller is configured to generate the strobe signal in response to a detection result of the occurrence of transmission error.

Device and method for driving display in response to image data

Device and method for driving display panel in response to image data

In an example, a processing system for an integrated display device and capacitive sensing device includes driver circuitry and a driver module. The driver circuitry is configured for coupling to a plurality of source lines and a plurality of sensor electrodes, where each of the plurality of sensor electrodes comprises at least one common electrode configured for display updating and capacitive sensing. The driver module is coupled to the driver circuitry and configured to drive the plurality of sensor electrodes for capacitive sensing during a first non-display update period that occurs between first and second display line update periods of a display frame, where the non-display update period is at least as long as one of the first and second display line update periods. The driver module is further configured to operate each of the plurality of source lines to reduce display artifacts during the non-display update period.

System and method for reducing display artifacts

Bandwidth management includes receiving, by a branch device, a requested display identification data structure from a display device. The branch device modifies the requested display identification data structure based on a total bandwidth through a constricted port on the branch device to obtain a modified display identification data structure. The branch device transmits the modified display identification data structure to a source device.

Branch device bandwidth management for video streams

An example method of performing capacitive sensing and display updating in an integrated capacitive sensing device and display device includes driving a plurality of display electrodes with one or more display voltages from one or more supplies during a first time period, the one or more voltages configured to drive the display pixels. The method further includes initiating a long horizontal blanking interval during a second time period. The method further includes driving a plurality of sensor electrodes with one or more sensing voltages from the one or more supplies during the second time period to perform capacitive sensing. The method further includes activating first circuitry during one of the first time period or the second time period to draw current to equalize power drawn from the one or more supplies during the first and second time periods within a threshold.

Optimizing pixel settling in an integrated display and capacitive sensing device

In one embodiment, a system includes one or more source drivers operable to drive a portion of a row or column of a display. The system also includes a timing controller coupled to each of the one or more source drivers and configured to control the one or more source drivers. The system further includes a downstream link for each of the one or more source drivers, configured to transfer data from the timing controller to one of the one or more source drivers. The system also includes an upstream link for each of the one or more source drivers, configured to transfer uplink data from one of the one or more source drivers to the timing controller, wherein the uplink data includes at least one of downlink lock status information and touch data.

Source driver uplink as indicator of downlink status

A method, signal conditioning circuit, and system are disclosed to perform signal conditioning using a processing component coupled with at least first and second inputs. The processing component is further coupled with a first output port including first and second data lanes operable at different data rates. The method includes receiving, via the first input and at a first data rate, data included in a first input signal, and receiving, via the second input and at a second data rate different from the first data rate, data included in a second input signal. The method further includes driving, based on the first and second input signals, a first output signal onto the first output port, which includes transmitting the data included in the first input signal on the first data lane, and transmitting the data included in the second input signal on the second data lane.

Signal conditioner for high-speed data communications

An example method of performing capacitive sensing and display updating in an integrated capacitive sensing device and display device includes driving a plurality of sensor electrodes of the capacitive sensing device for input sensing during a blanking period. The method further includes driving a plurality of source lines using a plurality of source drivers during the blanking period to update a first display line of the display device. The method further includes driving the plurality of source lines using the plurality of source drivers during a display update period to update one or more additional display lines of the display device. The method further includes adjusting an operational mode of the plurality of source drivers during the blanking period to equalize display pixel settling between the blanking period and the display update period.

A method for converting data signals from one power supply voltage domain for use in another power supply voltage domain. The method includes receiving the data signal at a first node of the integrated circuit, wherein the first node is within the first power supply voltage domain. The method also includes generating a first intermediate differential signal from the data signal via a first conversion circuit of the integrated circuit. The method further includes communicating the first intermediate differential signal to a first cross-coupled latch, wherein the first cross-coupled latch generates a first output signal based on the first intermediate differential signal. The method also includes outputting the first output signal from a second node of the integrated circuit, wherein the second node is in the second power supply voltage domain. Other embodiments, such as an integrated circuit, and an input device, are also provided.

Supply-modulation cross domain data interface

A data transmission system is provided. The data transmission system includes a source device having a source device controller and a register and a sink device having a sink device controller. The data transmission system also includes a transmission link coupling the source device and the sink device. The transmission link includes a unidirectional main line having a plurality of main link channels, a bidirectional auxiliary line configured to transmit data between the source device and the sink device at a first data rate, and a unidirectional interrupt line. The transmission link is configured to transmit data from the source device to the sink device over one of the main link lines at a second data rate and to transmit data from the sink device to the source device over the auxiliary line at the second data rate. The transmission link may comply with the DisplayPort standard, and the data may be transmitted in accordance with the USB standard.

System and method for transmitting USB data over a DisplayPort transmission link

An AUX channel amplifier for amplifying data in the AUX channel of a Display Port device. In some embodiments, the amplifier includes a first amplifier coupled to amplify a signal from a source to a sink and a second amplifier coupled to amplify a signal from the sink to the source. A slicer can be utilized to digitize the signal from the source. In some embodiments, a clock and data recovery can be utilized to receive signals from the source and a second clock and data recovery can be utilized to receive signals from the sink. A controller determine the direction of data flow and enables the first amplifier or the second amplifier accordingly.

Bi-directional channel amplifier

Rate matching for use in data links between a source device and a sink device is provided. A rate matching device includes a first-in-first-out (FIFO) buffer having a write pointer and a read pointer; a write control having a write clock to write an input data stream from the source device onto the FIFO buffer using the write pointer; a read control having a read clock to read data from the FIFO buffer using a read pointer, insert data to an output data stream and transmitting the data stream to the sink device; a processor to provide a bit number based on the write clock period and the read clock period, wherein the read control inserts blanking data into the output data stream while the read pointer is stopped in the FIFO buffer to allow the write pointer to move ahead by the bit number provided by the processor. Some embodiments are thus able to avoid buffer overflow or underflow scenarios.

Data rate buffering in display port links

A substrate biasing circuit may include a first pump control circuit that generates a first control signal in response to a first reference voltage and a voltage of a first substrate portion, and includes a first reference generator coupled between a temperature compensated voltage and a reference power supply voltage that varies the first reference voltage in response to the voltage of the first substrate voltage and the temperature compensated voltage. A first clamp circuit may generate a first clamp signal in response to a first limit voltage and the voltage of the first substrate portion, the first limit voltage being a scaled version of the temperature compensated voltage. A first charge pump may pump the first substrate portion in at least a first voltage direction in response to the first control signal, and is prevented from pumping in the first voltage direction in response to the first clamp signal.

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Cupertino, CA, United States of America

Prashant Shamarao