Intel Corporation

Synopsys, Inc.

Prashant Saxena

Pei-Hsin Ho

Satyanarayan Gupta

Mahesh A Iyer

Robert L Walker

Jing Chyuarn Lin

Sanjay Dhar

Vishal Khandelwal

Changge Qiao

Wei-Ting Chan

Kok Kiong Lee

Kumar Lalgudi

Thomas Robert Shiple

Prashant S Sawkar

Bala K Iyer

Stephen M Plaza

Sanjay V Kumar

Silvian Goldenberg

A routability optimization engine comprising a hotspot prediction engine to predict locations of a plurality of hotspots in a circuit layout based on a machine learning system, a white space calculator to calculate white space around each of the plurality of hotspots, and a cell spreader engine to redistribute white space around each of the plurality of hotspots to improve routability of the circuit layout.

Predictor-guided cell spreader to improve routability for designs at advanced process nodes

Systems and techniques are described for performing buffer tree synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during buffer tree synthesis.

Look-up based buffer tree synthesis

A multi-mode redundancy removal method is provided. In this method, after accessing the design, a full-scale redundancy removal using fault simulation can be started. When a predetermined period for performing the full-scale redundancy removal has reached a first cut-off, then the method can determine a location for temporary outputs of the design, create the temporary outputs, and perform a localized redundancy removal up to the temporary outputs. An optimized design based on the full-scale redundancy removal and the localized redundancy removal can be output.

Multi-mode redundancy removal

A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.

Interconnect-driven physical synthesis using persistent virtual routing

According to some embodiments, a noise problem is automatically analyzed within the context of a cell-based integrated circuit design to identify an adjustment to the design in view of the perturbation to the design caused by the adjustment.

Automated noise convergence for cell-based integrated circuit design

Described herein are two techniques referred to as 'Adaptive Power Routing' and 'Shield Sharing To Reduce Shield Count,' that allow power routing and signal routing to be integrated in a manner that provides more efficient and compact layout of design blocks as compared to traditional techniques. Adaptive power routing refers to completion of power routing to be postponed to the signal routing phase, at which time signal shielding requirements are also used to complete the power routing along with predefined power delivery constraints. Shield sharing optimization refers to the more efficient use of previously routed power lines and to the insertion of a reduced number of additional power lines so as to satisfy both shielding requirements and power supply requirements in a gridless environment. These two techniques allow routing in highly congested regions containing performance-critical and/or noise-sensitive signals to be manufactured using less die area than would be required with traditional routing methodologies and algorithms.

Adaptive power routing and shield sharing to reduce shield count

Provided are a method, system, and program for processing and verifying circuit designs. A circuit design specification written in a hardware definition language is received and zero delay black box code is added to the circuit design specification to position the zero delay black boxes at sequential elements. A synthesis of the circuit design specification is performed to generate a retimed implementation of the circuit design specification. The black boxes are processed in the retimed implementation to verify the synthesis of the circuit design.

Processing and verifying retimed sequential elements in a circuit design

Described herein are two techniques referred to as &ldquo;Adaptive Power Routing&rdquo; and &ldquo;Shield Sharing To Reduce Shield Count,&rdquo; that allow power routing and signal routing to be integrated in a manner that provides more efficient and compact layout of design blocks as compared to traditional techniques. Adaptive power routing refers to completion of power routing to be postponed to the signal routing phase, at which time signal shielding requirements are also used to complete the power routing along with predefined power delivery constraints. Shield sharing optimization refers to the more efficient use of previously routed power lines and to the insertion of a reduced number of additional power lines so as to satisfy both shielding requirements and power supply requirements in a gridless environment. These two techniques allow routing in highly congested regions containing performance-critical and/or noise-sensitive signals to be manufactured using less die area than would be required with traditional routing methodologies and algorithms.

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Portland, OR, United States of America

Prashant Saxena