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Prashant Rao

Martin Andreas Vorbach

Frank May

Armin Nückel

Volker Baumgarte

Gerd Ehlers

Frank Lier

Dirk Reichardt

Jens Oertel

An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Array processor having a segmented bus system

A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.

Data processor chip with flexible bus system

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Logical cell array and bus system

Logic cell array and bus system

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Munich, Germany

Prashant Rao