Intel Corporation

Prashant Ranjan

Jain Philip

Muralidharan S Chilukoor

Method and apparatus to perform cyclic redundancy check computations for error detection are described wherein a first stage includes a first set of computation elements, a first multiplexer and a second multiplexer. A latch is connected to the first stage. A second stage is connected to the latch and the second stage includes a second set of computation elements and a third multiplexer. The first stage and the second stage perform cyclic redundancy check computations for a packet, with the first set of computation elements performing cyclic redundancy check computations for a first set of bytes of input data from the packet, and the second set of computation elements performing cyclic redundancy check computations for a second set of bytes of input data from the packet. Other embodiments are described and claimed.

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Karnataka, India

Prashant Ranjan