Intel Corporation

Google Inc.

III Holdings 2, LLC

Prashant R Chandra

Weihuang Wang

Srinivas Vaduvatha

Uday Ramakrishna Naik

Alok Kumar

Kevin C Kahn

Jiazhen Zheng

Mark Bradley Davis

Sridhar Lakshmanamurthy

Abhishek Agarwal

Nandita Dukkipati

Efraim Kugman

Vladimir Yudovich

Eran Galil

Chen-Chi Kuo

Weiwei Jiang

Hugh McEvoy Walsh

Balakrishna Raghunath

Michael Dalton

Ameya S Varde

Ajay V Bhatt

Rohit Natarajan

Yuliang Li

Gautam Kumar

Jacob Adriaens

Hassan Wassel

Ian Mclaren

Jeen-Yuan Miin

Wilson Y Liao

Jon Olson

Thomas A Volpe

Mark B Rosenbluth

Amin Vahdat

Joseph Raymond Michael Zbiciak

Xiaoming Wang

Yim Pun

Niall Joseph Dalton

Vytautas Valancius

Eswar Eduri

Elli Bagelman

Horacio Andres Lagar Cavilla

Naama Zolotov

Yoni Dishon

David Alan Dillow

James D Guilford

Ren Wang

Michael E Kounavis

Christian Maciocco

Jaroslaw Sydir

Steven Bernard McGowan

James W Alexander

Michael Roger Marty

Raj S Yavatkar

Simon Luigi Sabato

Gurushankar Rajamani

Ahmad A Samih

Tsung-Yuan Charlie Tai

Hema Hariharan

Kin-Yip Liu

David Romano

Shrijeet Subhabrata Mukherjee

Harrick M Vin

Steve McGowan

Hassan Mohamed Gamal Hassan Wassel

Nicholas McDonald

Paul Burkley

Ye Tang

Masoud Moshref Javadi

Neelesh Bansod

Shrijeet Mukherjee

Pun Yim

Ajay Venkatesan

Behnam Montazeri

David Chou

Hugh Mcevoy Walsh

Nicholas Mcdonald

Jeen-Yuan Min

Wilson Liao

A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.

Efficient hash table lookup

Systems and methods of offloading multicast virtual network packet processing to a network interface card are provided. In an example implementation, a network interface card can route packets in a virtual network. The network interface card can be configured to receive a data packet having a multicast header for transmission to a plurality of destination virtual machines. The network interface card can retrieve a list of next hop destinations for the data packet. The network interface card can replicate the packet for each next hop destination. The network interface card can encapsulate each replicated packet with a unicast header that includes a next hop destination virtual IP address indicating the next hop destination and a source virtual IP address, and transmit the encapsulated packets.

Offloads for multicast virtual network packet processing in a network interface card

A packet cache system includes a cache memory allocator for receiving a memory address corresponding to a non-cache memory and allocated to a packet, and associating the memory address with a cache memory address; a hash table for storing the memory address and the cache memory address, with the memory address as a key and the cache memory address as a value; a cache memory for storing the packet at a location indicated by the cache memory address; and an eviction engine for determining one or more cached packets to remove from the cache memory and place in the non-cache memory when occupancy of the cache memory is high.

Packet cache system and method

Aspects of the disclosure are directed to supporting time synchronization across a datacenter network with greater accuracy. The time synchronization includes both software based and hardware based time synchronization mechanisms to provide more precise time synchronization across various nodes in the datacenter network. The software based mechanism can provide the initial coarse time synchronization while the hardware based mechanism can provide the subsequent finer time synchronization.

Mechanism for precise time synchronization in a datacenter network

The technology is directed to the use of a bitmap generated at a receiver to track the status of received packets sent by a transmitter. The technology may include a network device including an input port, output port, and circuitry. The circuitry may generate a transmitter bitmap that tracks each data packet sent to another network device. The circuitry of the network device may receive, from the other network device, a receiver bitmap that identifies each data packet that is received and not received from the network device. The circuitry may then determine which data packets to retransmit by comparing the transmitter bitmap to the receiver bitmap.

Early retransmission for hardware reliable transport

An application specific integrated circuit (ASIC) is provided for reliable transport of packets. The network interface card may include a reliable transport accelerator (RTA). The RTA may include a cache lookup database. The RTA may be configured to determine, from a received data packet, a connection identifier and query the cache lookup database for a cache entry corresponding to a connection context having the connection identifier. In response to the query, the RTA may receive a cache hit or a cache miss.

Off-chip memory backed reliable transport connection cache hardware architecture

A communication technology that provides for handling of failed packet transmissions to reduce retransmission attempts and uses resynchronization to prevent tearing down of connections. Thereby, providing for more resilient connections. In an implementation, an initiator entity may determine that a negative acknowledgment indicates that an operation for a particular packet is completed in error by a target entity, and transmit to the target entity a resynchronization packet without tearing down the connection.

Reliable transport protocol and hardware architecture for datacenter networking

A communication protocol system is provided for reliable transport of packets. A content addressable memory hardware architecture including an acknowledgment coalescing module in communication with a content addressable memory (CAM). The acknowledgment coalescing module coalesces multiple acknowledgement packets as a single acknowledgement packet to reduce the overall numbers of the packet transmission in the communication protocol system. In addition, the acknowledgment coalescing module may also provide a piggyback mechanism to carry acknowledge information in a regular data packet. Thus, the need to generate a new acknowledgement packet may be eliminated. Accordingly, the network congestion and latency may be reduced, and the communication and transmission efficiency are enhanced.

Acknowledgement coalescing module utilized in content addressable memory (CAM) based hardware architecture for data center networking

Aspects of the disclosure are directed to high performance connection cache eviction for reliable transport protocols in data center networking. Connection priorities for connection entries are determined to store the connection entries in a cache based on their connection priority. During cache eviction, the connection entries with a lowest connection priority are evicted from the cache. Cache eviction can be achieved with low latency at a high rate.

High performance cache eviction

A system includes a first processor configured to analyze packets received over a communication protocol system and determine one or more congestion indicators from the analysis of the data packets, the one or more congestion indicators being indicative of network congestion for data packets transmitted over a reliable transport protocol layer of the communication protocol system. The system also includes a rate update engine separate from the packet datapath and configured to operate a second processor to receive the determined one or more congestion indicators, determine one or more congestion control parameters for controlling transmission of data packets based on the received one or more congestion indicators, and output a congestion control result based on the determined one or more congestion control parameters.

Rate update engine for reliable transport protocol

A flow table management system can include a hardware memory module communicatively coupled to a network interface card. The hardware memory module is configured to store a flow table including a plurality of network flow entries. The network interface card further includes a flow table age cache configured to store a set of recently active network flows and a flow table management module configured to manage a duration for which respective network flow entries in the flow table stored in the hardware memory module remain in the flow table using the flow table age cache. In some implementations, age information about each respective flow in the flow table is stored in the hardware memory module in an age state table that is separate from the flow table.

Flow table aging optimized for DRAM access

A network interface card with traffic shaping capabilities and methods of network traffic shaping with a network interface card are provided. The network interface card and method can shape traffic originating from one or more applications executing on a host network device. The applications can execute in a virtual machine or containerized computing environment. The network interface card and method can perform or include several traffic shaping mechanisms including, for example and without limitation, a delayed completion mechanism, a time-indexed data structure, a packet builder, and a memory manager.

Fine grain traffic shaping offload for a network interface card

A communication protocol system is provided for reliable transport of packets. Transport of packets includes transmitting, by a sender entity over a connection to a receiver entity, a plurality of packets in a first order, maintaining, by the sender entity, one or more sliding windows including a plurality of bits, wherein each bit of the sliding window represents a respective packet of the plurality of packets, receiving, by the sender entity, one or more acknowledgments indicating that one or more of the plurality of packets have been received by the receiver entity, each of the acknowledgments referencing a respective packet of the plurality of packets and modifying, by the sender entity, values of one or more of the plurality of bits in the sliding window corresponding to the one or more acknowledgments received.

Growing community of inventors

Santa Clara, CA, United States of America

Prashant R Chandra