Intel Corporation

Micron Technology Incorporated

University of California

Infineon Technologies Ag

Nxp B.v.

Sematech, Inc.

International Business Machines Corporation

Prashant Majhi

Ravi Pillarisetty

Elijah V Karpov

Brian S Doyle

Abhishek A Sharma

Jack T Kavalieros

Niloy Mukherjee

Uday Shah

Wilman Tsai

Robert S Chau

Gilbert W Dewey

Marko Radosavljevic

Willy Rachmady

Kaan Oguz

Charles C Kuo

Chi On Chui

Mantu K Hudait

Titash Rakshit

Willman Tsai

Van H Le

Khaled Hasnat

Anup Pancholi

Patrick R Morrow

James S Clarke

Paul B Fischer

Khaled Ahmed

Kevin O'Brien

Tahir Ghani

Anand S Murthy

Glenn A Glass

Krishna Kumar Parat

Kunjal ShyamKumar Parikh

Kyu S Min

Justin Brockman

Aravind S Killampalli

Mark L Doczy

Chenming Hu

Kisik Choi

Richard M Fastow

David L Kencke

Ilya V Karpov

Roza Kotlyar

Niti Goel

Satyarth Suri

Markus Kuhn

Owen W Jungroth

Urusa Alaan

Arnab Sen Gupta

Hongfa Luan

Ryan E Arch

Huiying Liu

Yong Ju Lee

Mark R Brazier

Anupama Bowonder

Pratik Patel

Jaya P Gupta

Daniel Chou

Ali Khakifirooz

Han Wui Then

Sansaptak W Dasgupta

Benjamin Chu-Kung

Rafael Rios

Seung Hoon Sung

Derchang Kau

Yih Wang

Max F Hineman

Karthik Jambunathan

Rami Hourani

Husam N Alshareef

Daniel Bourne Aubertine

Deepak Thimmegowda

Tejaswi K Indukuri

Gopinath Bhimarasetti

Jeffery D Bielefeld

Seung-Chul Song

Ayan Kar

Susmita Ghose

Juan G Alzate Vinasco

Nicholas A Thomson

Byoung Hun Lee

Craig Henry Huffman

Heidi M Meyer

Pulkit Jain

Abhishek Sharma

Wei-Yip Loh

Jay P Gupta

Brian Coss

Benjamin Orr

Sang Ho Bae

Rino Choi

Rushabh Shah

William Tsai

Ashishek Sharma

Zhibo Zhang

Jong Hoan Sim

An integrated circuit structure includes a first non-planar semiconductor device and a second non-planar semiconductor device. The first non-planar semiconductor device includes a first body, a first gate structure at least in part wrapped around the first body, and a first source region and a first drain region. The first body extends laterally between the first source and first drain regions. The second non-planar semiconductor device comprises a second body, a second gate structure at least in part wrapped around the second body, and a second source region and a second drain region. The second body extends laterally between the second source and second drain regions. In an example, a first height of the first body is at least 5% different from a second height of the second body. Each of the first and second bodies can be, for instance, a nanoribbon, nanosheet, or nanowire.

Co-integration of high voltage (HV) and low voltage (LV) transistor structures, using channel height and spacing modulation

Described herein are integrated circuit (IC) devices that include devices that include fin-based field-effect transistors (FinFETs) integrated over gate-all-around (GAA) transistors. The GAA transistors may serve to provide high-performance compute logic, and may be relatively low-voltage transistors, while FinFETs may be more suitable than GAA transistors for providing high-voltage transistors, and, therefore, may serve to provide peripheral logic for backend memory arrays implemented over the same support structure over which the GAA transistors and the FinFETs are provided. Such an arrangement may address the fundamental voltage incompatibility by integrating a mix of FinFETs and GAA transistors in stacked complimentary FET (CFET) architecture to enable embedded 1T-1X based memories.

Integrated circuit devices with FinFETs over gate-all-around transistors

Integrated circuit (IC) assemblies with stacked compute logic and memory dies, and associated systems and methods, are disclosed. One example IC assembly includes a compute logic die and a stack of memory dies provided above and coupled to the compute logic die, where one or more of the memory dies closest to the compute logic die include memory cells with transistors that are thin-film transistors (TFTs), while one or more of the memory dies further away from the compute logic die include memory cells with non-TFT transistors. Another example IC assembly includes a similar stack of compute logic die and memory dies where one or more of the memory dies closest to the compute logic die include static random-access memory (SRAM) cells, while one or more of the memory dies further away from the compute logic die include memory cells of other memory types.

Integrated circuit assemblies with stacked compute logic and memory dies

Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

ESD protection decoupled from diffusion

A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises the first material, wherein the second structure is between the first and third structures.

Backend electrostatic discharge diode apparatus and method of fabricating the same

A memory device structure includes a vertical transistor having a channel between a source and a drain, a gate electrode adjacent the channel, where the gate electrode is in a first direction orthogonal to a longitudinal axis of the channel. A gate dielectric layer is between the gate electrode and the channel A first terminal of a first interconnect is coupled with the source or the drain, where the first interconnect is colinear with the longitudinal axis. The memory device structure further includes a pair of memory cells, where individual ones of the memory cells includes a selector and a memory element, where a first terminal of the individual ones of the memory cell is coupled to a respective second and a third terminal of the first interconnect. A second terminal of the individual ones of the memory cell is coupled to individual ones of the pair of second interconnects.

Pillar select transistor for 3-dimensional cross point memory

Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

Monolithic memory stack

An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

Apparatus with multi-wafer based device and method for forming such

A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.

Double-gated ferroelectric field-effect transistor

A transistor, including an antiferroelectric (AFE) gate dielectric layer is described. The AFE gate dielectric layer may be crystalline and include oxygen and a dopant. The transistor further includes a gate electrode on the AFE gate dielectric layer, a source structure and a drain structure on the substrate, where the gate electrode is between the source structure and the drain structure. The transistor further includes a source contact coupled with the source structure and a drain contact coupled with the drain structure.

Antiferroelectric gate dielectric transistors and their methods of fabrication

Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.

Thin film tunnel field effect transistors having relatively increased width

Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.

Thin-film-transistor based complementary metal-oxide-semiconductor (CMOS) circuit

AS-T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.

1S-1T ferroelectric memory

Ferroelectric field effect transistors (FeFETs) having band-engineered interface layers are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. A metal oxide material is on the semiconductor channel layer, the metal oxide material having no net dipole. A ferroelectric oxide material is on the metal oxide material. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.

Ferroelectric field effect transistors (FeFETs) having band-engineered interface layer

A memory cell is disclosed. The memory cell includes a storage component that includes a chalcogenide stack that includes a plurality of layers of material and a selector component that includes a Schottky diode.

3D memory array with memory cells having a 3D selector and a storage component

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San Jose, CA, United States of America

Prashant Majhi