Advanced Micro Devices Corporation

Prashant Jayaprakash Nair

David Andrew Roberts

Gabriel H Loh

Mark Richard Nutter

Michael Ignatowski

Mitesh Ramesh Meswani

John Robert Slice

A processing system includes a memory coupled to a processor. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.

Error detection and correction utilizing locally stored parity information

A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. Based on the indicators for the memory pages, the processor manages data at one or more levels of the processor's memory hierarchy.

Memory page access detection

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Prashant Jayaprakash Nair