International Business Machines Corporation

Prashant Jayaprakash Nair

Alper Buyuktosunoglu

Seokin Hong

Bulent Abali

Michael B Healy

Pradip Bose

Robert K Montoye

Ravi Nair

Bruce Martin Fleischer

Jeffrey Haskell Derby

Karthik V Swaminathan

Nandhini Chandramoorthy

Various embodiments are provided for enabling data compression in a computing system by a processor. Each storage block of a storage device associated with a queue may be split. Compression of data may be activated upon data occupancy within a queue exceeding a dynamic threshold. In one aspect, only a partial amount of the data is fetched, back to back, from a divided storage block in the storage block according to the queue based upon the data occupancy within the queue exceeding the dynamic threshold. A complete amount of the data may be fetched from the divided storage block in a storage block according to the queue upon the data occupancy within the queue being less than dynamic threshold.

Enabling compression based on queue occupancy

A method (and structure and computer product) to optimize an operation in a Neural Network Accelerator (NNAccel) that includes a hierarchy of neural network layers as computational stages for the NNAccel and a configurable hierarchy of memory modules including one or more on-chip Static Random-Access Memory (SRAM) modules and one or more Dynamic Random-Access Memory (DRAM) modules, where each memory module is controlled by a plurality of operational parameters that are adjustable by a controller of the NNAcc. The method includes detecting bit error rates of memory modules currently being used by the NNAccel and determining, by the controller, whether the detected bit error rates are sufficient for a predetermined threshold value for an accuracy of a processing of the NNAccel. One or more operational parameters of one or more memory modules are dynamically changed by the controller to move to a higher accuracy state when the accuracy is below the predetermined threshold value.

System and method for an error-aware runtime configurable memory hierarchy for improved energy efficiency

Single error correction ('SEC') code and triple error detection ('TED') code are used to optimize bandwidth and resilience under multiple bit failures. One or more errors in data stored in duplicated registers are detected and corrected using the SEC code and TED code where simultaneous read operations are produced with two copies of data for each of the duplicated registers for a multi-port banked memory array. The SEC code and TED code may be included in each of the two data copies of the simultaneous read operations.

Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures

Embodiments for mitigating cache-based data security vulnerabilities in a computing environment are provided. Cache pollution due to speculative memory accesses within a speculative path is avoided by delaying data updates to a cache and memory subsystem until the speculative memory accesses are resolved. A speculative buffer is used to maintain the speculative memory accesses such that a state of the cache remains unchanged until the speculative memory accesses are committed.

Microarchitectural techniques to mitigate cache-based data security vulnerabilities

Systems, methods and computer program products using multi-tag storage to enable efficient data compression in caches without increasing a tag/data area overhead. One method can comprise storing compressed versions of data elements in a data array of a cache, with tags for the compressed versions respectively appended to the compressed versions as stored in the data array, and storing hashed versions of the tags in a tag array of the cache, wherein the hashed versions of the tags respectively have fewer bits than the tags. A tag block may store hashed versions of tags corresponding to first and second compressed data elements stored in a cacheline of the cache. Hashed tag entries may be compared with full versions of the tags appended to compressed versions of data elements stored in the data array to prevent false positive cache reads. A compressed identifier (CID) may be stored with the hashed versions of tags in the tag array. Full versions of tags may be stored in the tag array for decompressed data stored in the data array of the cache.

Systems, methods and computer program products using multi-tag storage for efficient data compression in caches

A computer monitors a memory system during operation. The computer detects a first number of errors in the memory system. The computer determines that the first number of errors is below an error level threshold. The computer lowers a first group of one or more memory parameters of the memory system by a first amount. After the lowering of one or more memory parameters by the first amount, the computer detects a second number of errors in the memory system. The computer determines that the second number of errors is above the error level threshold. The computer raises a second group of one or more memory parameters of the memory system by a second amount.

Dynamic adjustments within memory systems

Embodiments include techniques for receiving a cacheline of data, hashing the cacheline into a plurality of chunks, wherein each chunk includes a pattern of bits, storing the plurality of chunks in a pattern table, wherein the plurality of chunks are indexed in the pattern table based on the pattern of bits of each chunk, and identifying a repeated pattern of bits of the plurality of chunks and selecting the repeated pattern of bits as candidate pattern. Techniques include comparing a threshold number of bits of the candidate pattern to the pattern of bits of the plurality of chunks in the pattern table; based on the comparison, inserting valid bits and a tag into the pattern table for the candidate pattern by replacing bits in the candidate pattern, and writing the candidate pattern, including the valid bits and the tag, into a location of the memory corresponding to the candidate pattern.

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Elmsford, NY, United States of America

Prashant Jayaprakash Nair