Intel Corporation

Prashant D Parmar

Johanna M Swan

Aleksandar Aleksov

Sujit Sharan

Feras Eid

Henning Braunisch

Kristof Darmawikarta

Yuan-Liang Li

Dong Zhong

Hyunjun Kim

Jung S Kang

Arnab Sarkar

Joel A Auernheimer

Jianggi He

Arghya Sain

Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

Via architecture for increased density interface

In an integrated circuit design, flex tape is used to provide signal ingress/egress to/from the integrated circuit design. Various architectures for the signal ingress/egress via flex tape is provided. In one embodiment, coaxial design is provided. In another embodiment, a coplanar waveguide design is provided.

Flex tape architecture for integrated circuit signal ingress/egress

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Gilbert, AZ, United States of America

Prashant D Parmar