Scintera Networks, Inc.

Rambus Inc.

Mosys, Inc.

Other

Inphi Corporation

Cadence Design Systems, Inc.

Jogurt, LLC

Nandanwar, Rupesh

Choudhary, Prashant

Prashant Choudhary

Qian Yu

Edem Ibragimov

Debanjan Mukherjee

Jishnu Bhattacharjee

Abhijit M Phanse

Abhijit G Shanbhag

Venugopal Balasubramonian

Charles Walter Boecker

Nanyan Wang

Fabian Giroud

Aldo Bottelli

Madabusi Govindarajan

Vadim Moshinsky

Nanyang Wang

Arvind Vijay Keerthi

Shaishav A Desai

Alvin Wang

Haidang Lin

Saman Behtash

Suresh Chandrasekaran

Venu Balasubramonian

An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate. The ISI estimate from each stage is further equalized by application of the measures of low-frequency ISI from the first feed-forward stage and fed to the next in the cascade of stages. The ISI estimates from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.

Multi-stage equalizer for inter-symbol interference cancellation

Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.

CTLE adaptation based on statistical analysis

An equalizer includes a first feed-forward stage that provides a measure of low-frequency IS I and a second feed-forward stage that includes a cascade of stages each making an IS I estimate. The IS I estimate from each stage is further equalized by application of the measures of low-frequency IS I from the first feed-forward stage and fed to the next in the cascade of stages. The IS I estimate from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.

Image analysis for comparison utilizes a combined image distance determined between the one or more captured images and the one or more reference images from a dual path analysis. The dual path analysis can comprise a first image analysis based on histograms of image colors and a second image analysis based a one-dimensional power spectral density of a black and white instance of the one or more captured images and the one or more reference images. In one case, the one-dimensional power spectral density derived by integrating a Discrete Fourier Transform of a two-dimensional image over annular rings of substantially equal area starting from the center of the two-dimensional image.

Image processing by determining combined image distances using dual path analyses

A yogurt maker device comprises an outer shell to house a yogurt vessel that receives milk and a culture container that receives yogurt culture. A processor within the outer shell controls a heating element to boil milk within the yogurt vessel using a temperature sensor as feedback and for maintaining a predefined boiling temperature for a predefined period of boiling time and a stirring device to continuously stir boiling milk within the yogurt vessel while boiling and also while cooling to a cooling predefined temperature until fermentation temperature is reached. The processor also controls a culture container base holding the culture container and having a motor to automatically pour the yogurt culture when the fermentation temperature is reached. Finally, a cooling mechanism automatically provides cooling to contents of the yogurt vessel once fermentation is complete.

Complete yogurt maker appliance

An automatic cooking device creates a recipe file based on an actual cooking session by an individual. The same dish can be automatically recreated on demand from the recipe file, wherein an optimal remaining cooking time is automatically determined responsive to an image analysis of real-time image sensor feedback versus reference image. In some implementations, recipe files are acquired through a network and downloaded for a fee.

Autonomous cooking device to prepare food from a recipe file and method for creating recipe files

Methods and circuits for analyzing a signal and adjusting parameters of an equalizer for a signal. The signal is received at a receiver over a channel wherein the signal has a wave form. The signal is equalized at an equalizer using an adjustable parameter for the equalization. Data points from the signal are sampled between upper and lower limits of a threshold at an error sampler. A performance metric of the signal is computed based on a statistical density of the data points from the signal between the upper and lower limits of the threshold.

Methods and circuits for adjusting parameters of a transceiver

A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.

Delay-locked loop with independent phase adjustment of delayed clock output pairs

Delay-locked loop with phase adjustment

A performance optimizing circuit is provided for a signal processing system which is parameterized by a set of coefficients that vary the operational characteristics of the signal processing system. The performance optimizing circuit receives as input a reference signal and an output signal of the signal processing system. The performance optimizing circuit may include (a) a cost computation circuit that receives the reference signal and the output signal and provides as output a cost signal representing a cost function computed using a set of current values for the set of coefficients, the output signal and the reference signal; and (b) a cost optimizer circuit that, at each of a plurality of successive time intervals, evaluates one or more values of the cost signal in the cost computation circuit and provides to the signal processing system a new set of values for the set of coefficients. The cost optimizer circuit implements two or more of the random search, parabolic interpolation and hill climbing techniques.

Method and apparatus to optimize adaptive radio-frequency systems

Systems and methods are disclosed to provide channel monitoring and/or performance monitoring for a communication channel. For example, in accordance with an embodiment of the present invention, an equalizer is disclosed that equalizes for channel distortions and also provides channel and performance monitoring information, such as for example bandwidth estimation, channel identification, signal-to-noise ratio, chromatic dispersion, and/or polarization-mode dispersion.

Channel monitoring and identification and performance monitoring in a flexible high speed signal processor engine

A continuous time equalizer for equalizing an input signal using a feedforward equalizer portion and a feedback equalizer portion is provided that includes: a slicer operable to make bit decisions on a combined output from the feedforward and feedback equalizer portions; an adaptive delay circuit operable to delay the combined output to form a delayed output; and a controller operable to control the delay provided by the adaptive delay circuit such that a first group delay through the slicer and a second group delay through the adaptive delay circuit in response to a sinusoidal form of the input signal are substantially equal.

Accurate timing alignments for decision directed continuous time equalizers

A continuous time electronic dispersion compensation architecture using feed forward equalization and a non-linear decision feedback equalization forms an output signal by a linear combination of successively delayed versions of the input signal and the sliced output signal weighted by appropriate coefficients. A selected number of taps in the mixer used to generate a corresponding number of coefficients for use in the feed forward equalizer are held to a selected voltage to ensure that the coefficients associated with these two taps do not drift. This causes the other coefficients to converge to a unique minimum square error value. In one embodiment the selected voltage is the maximum system voltage.

Method for robust and stable convergence of blind LMS based adaptation of coefficients for a continuous time FFE-DFE

A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer. The dynamic timing is controlled by a signal formed as a combination of feedback and feedforward signals. The feedback signal is an error signal related to a difference between pre-slicer and post-slicer signals. The feedforward signal is formed by differentiating and delaying the incoming data signal.

Growing community of inventors

Milpitas, CA, United States of America

Prashant Choudhary