Intel Corporation

Hitachi Micro Systems, Inc.

Hitachi America, Ltd.

Renesas Technology America, Inc.

Prasenjit Biswas

Kunio Uchiyama

Norio Nakagawa

Yi-Jen Chiu

Kevin Ray Iadonato

Gautam Dewan

Louis A Lippincott

Adrian R Pearson

Musa Jahanghir

Mei-Chen Yeh

Osamu Nishii

Shumpei Kawasaki

A system, apparatus, method, and article to process a chroma motion vector are described. The apparatus may include a video decoder. The video decoder includes a processor to receive a compressed video bitstream. The compressed video bitstream includes a stream of pictures. The stream of pictures includes a current slice and a current block within the slice. The processor pre-computes a chroma motion vector adjustment parameter for the current slice and determines a motion vector component for the current block within the current slice using the pre-computed chroma motion vector adjustment parameter.

Chroma motion vector processing apparatus, system, and method

Apparatus, systems and methods for hardware accelerated compressed video bitstream escape code handling are disclosed including an apparatus comprising a bitstream parser (BSP) to parse a bitstream of compressed video data. The BSP includes circuitry to extract uncompressed run and level data from the bitstream when the BSP detects an escape code in the bitstream. Other implementations are disclosed.

Hardware accelerated compressed video bitstream escape code handling

A system, apparatus, method, and article to process a flexible macroblock ordering and arbitrary slice ordering are described. The apparatus may include a video decoder. The video decoder includes a processor to store coding parameters of one or more neighboring macroblocks in a data buffer. The neighboring macroblocks are previously decoded macroblocks and are adjacent to a current macroblock. The processor is to store control parameters for each of the one or more neighboring macroblocks in the data buffer. The processor is to reconstruct coding parameters for the current macroblock using availability information associated with the neighboring macroblocks.

Flexible macroblock ordering and arbitrary slice ordering apparatus, system, and method

An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

Floating point unit pipeline synchronized with processor pipeline

A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing. Furthermore, data between the CPU and the FPU is transferred via a communication register. An FPU pipeline is synchronized with a CPU pipeline. The sixteen-bit fixed length instruction group has special instructions for immediate loading of a floating point zero and/or a floating point one. Two instructions are dedicated for this purpose. Furthermore, the 16-bit fixed length instruction group of the FPU flushes denormalized numbers to zero. The instruction set also rounds floating point numbers to zero. An FMAC instruction of the instruction set has the capability to accumulate into a different register for consecutive FMAC operations.

Microprocessor including floating point unit with 16-bit fixed length

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Saratoga, CA, United States of America

Prasenjit Biswas