Cosmic Circuits Private Limited

Maxlinear, Inc.

Cadence Ams Design India Private Limited

Cirel Systems Private Limited

Prasenjit Bhowmik

Prakash Easwaran

Sundararajan Krishnan

Sriram Ganesan

Sumeet Mathur

Sumanth Chakkirala

Prasun Kali Bhattacharya

Chandrashekar Lakshminarayanan

Mukesh Khatri

Sanjeeb Kumar Ghosh

Rishi Mathur

Abhishek Ghosh

Chakravarthy Srinivasan

Prasun Kali Bhattacharyya

Leela Madhav Lakkimsetti

Subramanian Anantharaman Chandrasekarapuram

Venkatesh Teeka Srinivasa Shetty

Raghavendra Rao Haresamudram

Srinivasan Chakravarthy

Venkatesh Teeka Srinvasa Setty

G Sriram

Praveen Ghanashyam Shekokar

Jyoti Arya

Sameer Madhav Gandhi

Sunil Rajan

A system for a radio access network (RAN) includes a radio unit (RU) configured to receive first in-phase and quadrature (I/Q) data represented in a first domain from a distributed unit (DU). The system includes a beamformer associated with the RU. The beamformer is configured to receive the first I/Q data represented in the first domain. The beamformer is also configured to transmit second I/Q data represented in the first domain based on the first I/Q data in the first domain. The system also includes a transceiver associated with the RU. The transceiver is configured to receive the second I/Q data represented in the first domain. The transceiver is also configured to convert the second I/Q data represented in the first domain to second I/Q data represented in a second domain.

Data transfer interface for in-phase and quadrature (I/Q) data

Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

Clocking scheme in nonlinear systems for distortion improvement

A switching regulator circuit includes a gate driver circuit driving a first switch and a second switch to generate a first voltage at a first node. Further, the switching regulator includes an LC filter circuit responsive to the first voltage to generate a desired output voltage. Moreover, the switching regulator includes a regulator circuit coupled to the LC filter circuit to control the gate driver circuit. The regulator circuit accurately controls variations in trip point. The trip point is a voltage at which the second switch is switched OFF by the gate control circuit. The regulator circuit includes one of a Delay Locked Loop (DLL) and a Pulse width modulator (PWM) controller.

Accurate zero current detector circuit in switching regulators

The main feedback loop of a PLL/DLL receives a reference clock and an output clock as inputs, and operates to achieve one or both of a phase and a frequency lock of the output clock with respect to the reference clock. The PLL/DLL includes an RS-latch connected to receive the output clock and the reference clock. The RS-Latch generates a digital output representing a phase difference between the reference clock and the output clock. A correction block in the PLL/DLL receives the digital output and adjusts an electrical characteristic of the main feedback loop by a value that is based on a polarity of the digital output. Effects of offset-errors in the PLL/DLL are thereby minimized or corrected for.

Correcting for offset-errors in a PLL/DLL

A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.

Relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation

A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.

DC biasing circuit for a metal oxide semiconductor transistor

A current filter circuit is provided. The current filter circuit comprises a source transistor comprising a drain, a gate, and a source. The source of the source transistor is coupled to a reference voltage terminal, the gate of the source transistor is coupled to the gate of a mirror transistor, and the drain of the source transistor is coupled to a reference current source. The mirror transistor comprises a drain, a gate, and a source. The source of the mirror transistor is coupled to the reference voltage terminal, the gate is coupled to the gate of the source transistor, and the drain is coupled to a load. The current filter circuit comprises a low pass filter for filtering noise. The current filter circuit also comprises an impedance reduction circuit coupled to the drain of the mirror transistor for reducing bandwidth of the current filter circuit.

Leakage independent very low bandwith current filter

A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

System and method for reducing power dissipation in an analog to digital converter

A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.

Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof

A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Delay line with delay cells having improved gain and in built duty cycle control and method thereof

A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.

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Bengaluru, India

Prasenjit Bhowmik