Xilinx, Inc.

Reniac, Inc.

Marvell Asia Pte., Ltd.

Other

Prasanna Sundararajan

Chidamber Kulkarni

Brandon Blodget

Scott P McMillan

Eric R Keller

Philip Bryn James-Roxby

David W Bennett

Prasanna Sukumar

Steven A Guccione

Cameron D Patterson

Jeffrey M Mason

Raushan Raj

Rahul Sachdev

Bernard J New

Tim Tuan

Adam P Donlin

Derek R Curd

Andrew Richard Putnam

Ian L McEwen

Rahul N Jain

Pradeep Mishra

Richard J LeBlanc

Punit S Kalra

Vincent P Eck

Amarnath Vishwakarma

Aditya Alurkar

Carter Hamilton

Vijaya Raghava

Gurshaant Singh Malik

Ajit Mathew

Stephen M Trimberger

Robert D Turney

Trevor J Bauer

Paul R Schumacher

Jorn W Janneck

Carl H Carmichael

Jeffrey V Lindholm

Robert Gwilym Dimond

John D Corbett

Mark Paluszkiewicz

Syam Prasad

Lauren B Wenzl

Stephen W Trynosky

Murali Krishna

Ashutosh Sharma

Vijaya Raghava Chiyedu

Kuladeep Sai Reddy

Vaibhav Jain

Philip B James-roxby

Richard J Leblanc

Scott P Mcmillan

Brandon J Blodget

A database proxy includes a computing device and a hardware-accelerated database proxy module. The computing device and the database proxy module. The database proxy is configured to receive a write request from a client; store the write request in a commit log in a first non-volatile memory device; in response to storing the write request in the commit log, return to the client a signal acknowledging success of the write request; store the write request in a cache in a second non-volatile memory device; cause the write request to be written in a database store; and based on a first determination that the write request is stored in the cache and on a second determination that the write request is written in the database store, remove the write request from the commit log.

Persistence of write requests in a database proxy

A database proxy includes a computing device and a hardware-accelerated database proxy module. The computing device includes one or more processors, memory, a first bus interface, and a network interface coupling the database proxy to one or more networks. The database proxy module includes a second bus interface coupled to the first bus interface via one or more buses, and a request processor. The database proxy is configured to receive a database read request from a client via the one or more networks and the network interface; forward the database read request to the request processor using the one or more buses; process, using the request processor, the database read request; and return results of the database read request to the client. In some embodiments, the computing device or the database proxy module further includes a flash memory interface for accessing one or more flash memory devices.

System and method for a database proxy

Techniques for accelerating compaction include compaction accelerator. The compaction accelerator includes a compactor separate from a processor performing read and write operations for a database or a data store. The compactor includes a plurality of compaction resources. The compactor is configured to receive a compaction request and data to be compacted, compact the data via a compaction pipeline to generate compacted data, and forward the compacted data to the processor, the database, or the data store. The compaction pipeline has a first portion of the plurality of compaction resources.

Techniques for accelerating compaction

A system and method for accelerating compaction includes a compaction accelerator. The accelerator includes a compactor separate from a processor performing read and write operations for a database or a data store. The compactor is configured to receive a table to be compacted and entries written in the table, each of the entries being associated with a timestamp indicating when they were respectively written; identify, using a plurality of sort engines operating in parallel, the entries that were written last based on the timestamps; mark, using a plurality of marker engines operating in parallel, older copies of the entries for deletion; create, using the plurality of marker engines, tombstones for the older copies; create a compacted table, including the entries that were last written; delete the tombstones and the entries associated with the tombstones; and generate a freemap based on storage locations of the entries associated with the tombstones.

System and method to accelerate compaction

A database proxy includes a request processor, a cache, a database plugin, and interfaces for coupling the database proxy client devices, other database proxies, and database servers. The request processor is configured to receive a read request from a client, determine whether the read request is assigned to the database proxy, and return results of the read request to the client. When the read request is not assigned to the database proxy, the read request is forwarded to another database proxy. When the read request is assigned to the database proxy, the read request is processed using data stored in the cache when the results are stored in the cache or forwarded to the database plugin, which forwards the read request to a database server, receives the results from the database server, and returns the results to the request processor for storage in the cache.

A system includes a field-programmable gate array (FPGA) with a configurable logic module. The configurable logic module is configured to implement a protocol endpoint, the protocol endpoint including a congestion control module. In some examples, the protocol endpoint corresponds to a transport control protocol (TCP) endpoint. In some examples, state information associated with a networking protocol implemented by the protocol endpoint is stored in and retrieved from block memory of the configurable logic module. In some examples, no state information associated with the networking protocol is stored in and retrieved from a memory other than the block memory. In further examples, the congestion control module is configured to perform operations comprising monitoring a congestion condition of a network and dynamically switching among a plurality of congestion control algorithms based on the monitored congestion condition.

Systems and methods for congestion control in a network

A disclosed stream memory management circuit includes a first memory controller circuit for accessing a first memory of a first type. A second memory controller circuit is provided for accessing a second memory of a second type different from the first type. An access circuit is coupled to the first and second memory controller circuits for inputting and outputting streaming data. An allocation circuit is coupled to the access circuit, the allocation circuit configured and arranged to select either the first memory or the second memory for allocation of storage for the streaming data in response to attributes associated with the streaming data. A de-allocation circuit is coupled to the access circuit for de-allocating storage assigned to the streaming data from the first and second memories.

Stream memory management unit (SMMU)

Approaches for generating and operating an electronic system. High-level language (HLL) source code is compiled into equivalent intermediate language program code. The compilation determines a plurality of caches for storing data referenced by the HLL source. Flush instructions are inserted in the intermediate language program. Each flush instruction references one of caches and is inserted in the intermediate language program immediately following an instruction that is last to write to that cache. The intermediate language program is translated into a hardware description that specifies the plurality of caches, circuits for processing data in the caches, and for each of the caches a flush interface that initiates writing data from the cache to a main memory in response to a flush signal. The timing of the respective flush signal is determined based on placement of one of the one or more flush instructions in the intermediate language program.

Compiler directed cache coherence for many caches generated from high-level language source code

A heterogeneous memory system includes a main memory arrangement, a first-level cache, a second-level cache, and a memory management unit (MMU). The first-level cache includes an SRAM arrangement and the second-level cache includes a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the first-level cache or the second-level cache for storage of the first data and stores the first data in the selected one of the first or second-level caches. The MMU reads second data from one of the first-level cache or second-level cache and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.

Heterogeneous memory system

A heterogeneous memory system includes a network interface card, a main memory arrangement, a first-level cache, and a memory management unit (MMU). The main memory arrangement, first-level cache and the MMU are disposed on the network interface card. The first-level cache includes an SRAM arrangement and a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the SRAM arrangement or the DRAM arrangement for storage of the first data and stores the first data in the selected one of the SRAM arrangement or DRAM arrangement. The MMU reads second data from one of the SRAM arrangement or DRAM arrangement and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.

A heterogeneous memory system includes a main memory arrangement, a first-level cache, and a memory management unit (MMU). The first-level cache includes an SRAM arrangement and a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the SRAM arrangement or the DRAM arrangement for storage of the first data and stores the first data in the selected one of the SRAM arrangement or DRAM arrangement. The MMU reads second data from one of the SRAM arrangement or DRAM arrangement and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.

Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.

Generation of cache architecture from a high-level language description

Approaches for creating a pipelined circuit design from a high level language (HLL) specification. In one embodiment, the HLL specification is translated into an intermediate level language specification of operations of the pipelined circuit design, and a data dependency graph of the operations is created. A sequence of operations that is bounded by two write operations and that has no intervening write operations between the two write operations is identified, along with two or more read operations within the sequence. A pipelined design specification is generated from the dependency graph and hardware components associated with the operations in the intermediate level language specification. At least two of the components corresponding to the two or more read operations access a memory in parallel, and each component corresponding to the two or more read and the two write operations requires a synchronization token as input and outputs a synchronization token upon completion of the operation.

Synchronization of parallel memory accesses in a dataflow circuit

Approaches for generating a hardware specification from a high-level language (HLL) program. In one approach, a method determines separate accesses in the HLL program to multiple consecutively addressed data items. The HLL program is compiled into an intermediate language program to include one or more instructions that perform functions on the multiple consecutively addressed data items and one or more memory access instructions that reference the consecutively addressed data items. The method generates a hardware specification from the intermediate language program. The hardware specification includes a cache memory that caches the consecutively addressed data items and that accesses the consecutively addressed data items in response to a single access request. The specification further includes one or more hardware blocks that implement the functions of the instructions in the intermediate language program. At least one of hardware blocks has access to the multiple consecutively addressed data items in parallel.

Optimization of cache architecture generated from a high-level language description

Growing community of inventors

Mountain View, CA, United States of America

Prasanna Sundararajan