Micron Technology Incorporated

Intel Corporation

Prasanna Srinivasan

Roger W Lindsay

John David Hopkins

Fatma Arzum Simsek-Ege

Hongbin Zhu

Zhenyu Lu

Jie Sun

Purnima Narayanan

Brian J Cleereman

Anton J deVillers

Scott L Light

David A Kewley

Hongqi Li

Jianming Zhou

Zailong Bian

Jin Lu

Gowrisankar Damarla

Shyam Ramalingam

Pranav Kalavade

Owen W Jungroth

Sung-Taeg Kang

Apparatus, systems, or methods for a memory array having a plurality of word lines. A word line includes at least one word line plate, and the word line plate comprises a first material with a first resistivity. An edge of the word line plate is recessed and filled with a second material having a second resistivity that is lower than the first resistivity. As a result, the total resistance of the word line may be reduced compared to a word line using only the first material with the first resistivity. Other embodiments may also be described and claimed.

Resistance reduction for word lines in memory arrays

Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Methods and apparatuses having memory cells including a monolithic semiconductor channel

A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition or other process to prevent polishing down the conductive material to isolate the contacts. The conductor channel extends through a deck of multiple tiers of circuit elements that are activated via a gate. The gate is activated by electrical potential in the conductor channel. The conductive cap on the conductor channel can electrically connect the conductor channel to a bitline or other signal line, and/or to another deck of multiple circuit elements.

Capping poly channel pillars in stacked circuits

Methods of lithography, methods for forming patterning tools, and patterning tools are described. One such patterning tool include an active region that forms a first diffraction image on a lens when in use, and an inactive region that forms a second diffraction image on a lens when in use. The inactive region includes a pattern of phase shifting features formed in a substantially transparent material of the patterning tool. Patterning tools and methods, as described, can be used to compensate for lens distortion from effects such as localized heating.

Lithography methods, methods for forming patterning tools and patterning tools

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Boise, ID, United States of America

Prasanna Srinivasan