International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Prasanna Jayaraman

Anand Haridass

Daniel Mark Dreps

Tony Emile Sawan

Gary A Tressler

M Dean Sciacca

Janani Swaminathan

Frank David Ferraiolo

Robert Walter Berry, Jr

Girisankar Paulraj

Trinadhachari Kosuru

Timothy Jay Dell

Manoj Dusanapudi

Anil Bindu Lingambudi

Saurabh Chadha

Abhijit Saurabh

Diyanesh B Chinnakkonda Vidyapoornachary

Nam Huu Pham

Charles Francis Marino

David John Krolak

Srinivasan Ramani

Irving G Baysah

Srinivas Bangalore Purushotham

Diyanesh Babu C Vidyapoornachary

Vijay Anand Mathiyalagan

Pavel Roy Paladhi

Diyanesh B Chinnakkonda

Diyanesh Babu Vidyapoornachary Chinnakkonda

Erich Jurg Hauptli

Eakambaram Rangaswamy Thirumalai

Saravanan Sethuraman

Rahul Rao

Michael B Spear

Diyanesh B Vidyapoornachary

Khajistha Fattu

Robert W Berry

Michael Fattu

Eakambaram R Thirumalai

A computer controls voltage supply for a system that includes a plurality of active cables. The computer determines that a first voltage source included in a first cable has failed to provide a required amount of voltage to the first cable. The computer switches the first cable to a second voltage source included in a second cable. The second voltage source provides voltage to the first cable.

Redundant voltage delivery with active cables

A computer uses an active cable architecture to control communications. The computer sends a first set of instructions for completion of an activity to a first micro-controller of an active communication cable. The computer determines that at least one transceiver of an active cable is to receive a set of signals from the first micro-controller. The computer forms a communication connection between the first micro-controller and the at least one transceiver. The computer sends a second set of instructions to the at least one transceiver, wherein the second set of instructions instruct the at least one transceiver to complete at least a portion of the activity.

Architecture with micro-controller and high-speed active cables

A method, system, and/or computer program product controls transitions from a first bandwidth to a second bandwidth in a bus within a multi-processor computer. A bus controller predicts a bandwidth transition requirement for a bus in a multi-processor computer, and transitions the bus from a first bandwidth to a second bandwidth based on the predicted bandwidth transition requirement. The bus controller checks an actual transitioning requirement of the bus in the computer, such that the bus controller checks the actual transitioning requirement for the bus at each occurrence of a predefined stage of operation of one or more processor processors in the computer. In response to the actual transitioning requirement matching the predicted bandwidth transition requirement, the bus controller directions a continuation of the transitioning of the bus from the first bandwidth to the second bandwidth.

Staged power on/off sequence at the I/O phy level in an interchip interface

A method, executed by a computer, includes pairing a first core with a second core to form a first core group, wherein each core of the group has a plurality of functional units, transferring instructions received by the first core to the second core for execution via a first inter-core communication bus, and executing the instructions on the second core. A computer system and computer program product corresponding to the above method are also disclosed herein.

Core pairing in multicore systems

A method, a system and a computer program product for supporting a reconfigurable hardware network topology including graphics processor units (GPU) and central processing unit (CPU) interconnectivity. The re-configurability of the network is based on data bandwidth and latency requirements of running workloads obtained by running training workload sequences upon the configured topology. For network re-configurability, a user enabled to directly connect high-speed cable links between CPU/GPU connectors and between GPU/GPU connectors. Further included in a configured network topology are switches configurable to provide one or more PCIe high-speed side-band links, as well as a high speed multiplexor, that can switch the network topology. The method prepares a system map of the hardware network topology, and generates a GPU weightage pattern based on data bandwidth and latencies of the configured GPUs such that GPUs are assigned to workloads based on its weightage to optimize workload performance.

Reconfigurable network infrastructure

An apparatus for cognitive data center management is disclosed. A computer-implemented method and computer program product also perform the functions of the apparatus. According to an embodiment of the present invention, the apparatus includes a performance module that determines performance metrics over a predetermined time interval at a device coordinate in a three-dimensional ('3D') coordinate system for each replaceable device of a plurality of replaceable devices within a data center. The apparatus maps the performance metrics to environmental sensor measurements taken in the 3D coordinate system. The apparatus further includes an input analysis module that uses discovery analytics to determine a predicted time to failure for each replaceable device. The apparatus further includes a preventative action module that determines recommended actions to prevent failure of the replaceable devices and a tradeoff learning module that provides updated weighting factors based on changes to performance metrics in response to taking recommended actions.

Cognitive data center management

A method, a system and a computer program product for reconfiguring hardware network topology including graphics processor units (GPU) and central processing unit (CPU) interconnectivity on or across compute nodes of a rack-mount server. The re-configurability is based on detected thermal throttling or thermal hot spots when running workloads. For network re-configurability, a user can directly connect high-speed cable links between CPU/GPU connectors and between GPU/GPU connectors on a same PCB compute node, or across two PCB compute nodes as suggested by a control processor to avoid thermal and power hotspots when running the workload. The method recommends and generates a system map of the hardware network topology known to avoid/mitigate thermal throttling, and instructs a configuration of CPUs and GPUs such that GPUs are assigned to workloads at locations for mitigating thermal throttling based on detected thermal hot spots and power hot spots to optimize workload performance.

Reconfigurble CPU/GPU interconnect to mitigate power/thermal throttling

Examples of techniques for memory transaction prioritization for a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method includes allocating, by a memory controller, a reserved portion of the memory controller to execute transactions. The method further includes receiving, by the memory controller, a priority based transaction from a processor to the memory. The method further includes determining, by the memory controller, whether to accommodate the priority based transaction based at least in part on a current processing state of the memory controller. The method further includes, based at least in part on determining to accommodate the priority based transaction, accommodating the priority based transaction by performing at least one of dropping a speculative command in a queue or using the reserved portion of the memory controller to execute the priority based transaction.

Memory transaction prioritization

It is determined that a guard band frequency for a first processor is to be determined. The guard band frequency is associated with a first system configuration. A validation start frequency is determined based, at least in part, on data associated with at least one of the first processor or a second processor. The validation start frequency is between a nominal operating frequency for the first processor and a system maximum operating frequency for the first processor. A guard band frequency for the second processor was previously determined. The guard band frequency for the first processor is determined based, at least in part, on the validation start frequency.

Frequency guard band validation of processors

Methods, apparatuses, and products for budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements ('ITEs'), each ITE having power utilization information indicating an average power consumption of the ITE, including: determining, by a chassis management module, a total power requirement value based on a sum of the average power consumption for each ITE; increasing, by the chassis management module, the total power requirement value in dependence upon a predetermined power utilization delta; identifying, by the chassis management module, one or more power supplies to provide power to the ITEs in the chassis environment in dependence upon power delivery capabilities of the one or more power supplies and the total power requirement value; and powering on the identified one or more power supplies by the chassis management module.

Budgeting for power consumption in a chassis environment that includes a plurality of integrated technology elements

Remapping software elements to increase the usability of a device with a damaged screen including receiving a request to transition the device with the damaged screen into damaged screen mode; dividing, by a remapping module, the damaged screen into a plurality of sectors; determining, by the remapping module, a usability of each of the plurality of sectors of the damaged screen; remapping, by the remapping module, elements of device software to sectors based on the usability of each of the plurality of sectors of the damaged screen; and presenting the remapped elements of the device software to a user of the device.

Remapping software elements to increase the usability of a device with a damaged screen

Examples of techniques for memory transaction prioritization for a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: The method may further include: allocating, by a memory controller, a reserved portion of the memory controller to process prioritized transactions; receiving, by the memory controller, a request transaction from a processor to the memory, wherein the request transaction comprises a priority; determining, by the memory controller, whether the priority of the request transaction is above a priority threshold; and responsive to determining that the priority of the request transaction is above the priority threshold, executing the request using the reserved portion of the memory controller.

A solid state disk (SSD) device has a set of data transfer parameters which regulate I/O operations of the SSD device. The temperature of the SSD device is monitored using temperature readings from a temperature sensor. The temperature of the SSD device satisfies a temperature threshold. A data transfer modification is determined. The data transfer modification is capable of modifying one or more data transfer parameters of the set of data transfer parameters. The set of data transfer parameters is modified using the data transfer modification in response to the temperature of the SSD satisfying the temperature threshold. One or more I/O operations are completed with the SSD device using the modified set of data transfer parameters.

Managing temperature of solid state disk devices

Growing community of inventors

Bengaluru, India

Prasanna Jayaraman