Lsi Logic Corporation

Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Prasad Subbarao

Bo Shen

Radoslav Ratchkov

Thomas Mathews Antisseril

Maad A Al-Dabagh

Charutosh Dixit

Manjunatha Gowda

Prabhakaran Krishnamurthy

Hiroshi Ishikawa

Gregory W Sheets

Ramnath Venkatraman

Anwar Ali

Sandeep Bhutani

Vishwas M Rao

James C Parker

Benjamin Mbouombouo

Weidan Li

Thai Minh Nguyen

Saket K Goyal

Ruben Salvador Molina

Clayton E Schneider, Jr

Julie Beatty

Santhanakrishnan Raman

Qiong J Yu

Lihui Cao

Hai H Tan

David Gradin

In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode.

Closed-loop adaptive voltage scaling for integrated circuits

Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.

Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby

A method and system for predicting delay of a multi-million gate sub-micron ASIC design is disclosed. The method and system include automatically partitioning a netlist into at least two logic cones, and running respective instances of a delay prediction application on the logic cones on at least two computers in parallel.

Distributed delay prediction of multi-million gate deep sub-micron ASIC designs

A method for modeling the output waveform of a cell driving a resistance-capacitance network includes multiple effective capacitances. A method of calculating Thevenin parameters includes the steps of (a) initializing estimates of effective capacitances Ceff1 and Ceff2, of a switching threshold delay t0, and of a slope delay deltat; (b) solving ramp response equations for t0 and deltat as a function of Ceff1 and Ceff2; (c) comparing the estimates of t0 and deltat with solutions for t0 and deltat found in step (b); and (d) replacing the estimates of t0 and deltat with the solutions for t0 and deltat if the solutions for t0 and deltat have not converged to the estimates of t0 and deltat.

Driver waveform modeling with multiple effective capacitances

A multiple layer power mesh design includes an L-shaped structure and a bow tie-shaped structure. The L-shaped structure provides a plurality of L-shaped power rails in each of four quadrants of the layer. The bow tie-shaped structure includes plurality of vertical power rails in each of a left and right triangularly-shaped portion of the layer. The vertical power rails of the bow tie-shaped structure provide and interface between the upper and lower quadrants of the L-shaped layer. The bow tie-shaped structure provides additional available space which can, for example, be used for routing signal traces. A T-shaped structure is also provided for use with the bow tie-shaped layer. The T-shaped layer provides for improved distances between the VDD and the VSS power rails.

Bowtie and T-shaped structures of L-shaped mesh implementation

A method for checking power errors in an ASIC design is disclosed. The method includes providing a power checker software program with one or more power checker modules that each check a particular type of power element in the ASIC design. A power checker database is created that stores the following: individual power elements in the ASIC design, a connectivity graph of the power elements, and location bins corresponding to physical areas in ASIC design that identify the power elements that are located within each area. The method further includes providing a user with a choice of which power elements in the design to check, and executing the power checker modules corresponding to the selected power elements in order to check for errors in the selected power elements. Finally, any detected errors are output for the user.

Method and system for checking for power errors in ASIC designs

A method for estimating decoupling capacitance during an ASIC design flow is disclosed. The method includes precharacterizing a set of power grid structures to model their respective noise behaviors, and storing the respective noise behaviors as noise factors in a table. During the ASIC design flow for a current design that includes at least one of the precharacterized power grid structures, the corresponding noise factor from the table is used to calculate decoupling capacitance for the current design.

Decoupling capacitance estimation and insertion flow for ASIC designs

A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.

Donut power mesh scheme for flip chip package

A rectangular termination ring for a power distribution mesh is placed on the upper two layers of an integrated circuit and may be placed over some I/O circuitry. The strapping connecting the bonding pads to the termination ring are placed on upper levels of the integrated circuit, minimizing the via requirements and freeing space for additional circuitry. Further, the termination ring may be adapted to work in conjunction with L-shaped, as well as other power distribution meshes.

Termination ring for integrated circuit

Growing community of inventors

San Jose, CA, United States of America

Prasad Subbarao