Cypress Semiconductor Corporation

Prasad Rao Kotra

Victor Simileysky

David William Moeller

Stephen W Dow

Radhika Venkatasubramanian

Ataur Rehman Khan

Brian Ballweber

Pulkit Shah

Shailesh Shah

Sunil Thamaran

Apparatuses and methods of operating a flexible and optimized power management unit (PMU) for multiple power supply scenarios are described. One integrated circuit includes a first terminal to couple to an unregulated power supply, a second terminal to couple to a regulated power supply, a first regulator, and a second regulator. The first regulator outputs a first supply voltage in a first configuration, and the second regulator outputs a second supply voltage in a second configuration. The first and second regulators do not operate concurrently.

Flexible and optimized power management unit (PMU) for multiple power supply scenarios

An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.

Pull-up circuit for an input buffer

A programmable low voltage reset apparatus for a device having a plurality of power supplies comprises a low voltage signal generator for sensing when a power supply output decreases below a predetermined voltage and generating a reset signal, a reset selector for selecting one of the power supplies, and a programmable reference voltage for varying a reference voltage according to the voltage of the selected power supply.

Programmable low voltage reset apparatus for multi-Vdd chips

An apparatus including a driver and an adjustment circuit. The driver circuit may be configured to generate an output signal in response to a clock input signal and an adjustment signal. The adjustment circuit may be configured to generate the adjustment signal in response to the output signal. The adjustment signal may be configured to correct a duty cycle of the output signal.

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Bengaluru, India

Prasad Rao Kotra