Intel Corporation

Google Inc.

Alliance Semiconductor Corporation

Tundra Semiconductor Corporation

Prasad Modali

Mohammad A Abdallah

Nirmal Raj Saxena

Olivier Jean Benoit

Vinoth Kumar Deivasigamani

Shreekant S Thakkar

Yu Huang

Patrice L Roussel

Vladimir M Pentkovski

Thomas R Huff

Uma M Gadamsetty

Benjamin K Dodge

Kamal J Koshy

Sudhir Kumar Singh

Jose M Rodriguez

John C Wei

Raghavan Sudhakar

Chien-Yu Huang, Legal Representative

Abhishek Narain

Anil Babu Nangunoori

This document describes a secure element that leverages the resources of a computer system to perform specialized functions using sensitive information. The secure element securely stores sensitive information on flash memory of the computer system. In response to a request requiring use of sensitive information, the secure element loads a security application and sensitive information from the computer system. By leveraging external resources, the secure element may flexibly accommodate increasing resource requirements of the computer system and be used in a wide range of computer systems.

Secure element that leverages external resources

If a secure element accesses a resource that is separate from the secure element, conducting a secure transaction can be inefficient in terms of power or time. Power usage is inefficient if the resource is never permitted to sleep, and transaction time is inefficient if the resource is permitted to sleep, and the user experiences a delay. To enable dual efficiency, a resource entity is permitted to be powered down. The resource entity is then powered up speculatively by an activation controller. The activation controller predicts an upcoming secure transaction based on sensor output, such as a position fix or a detected electromagnetic field. Based on monitored sensor output, the activation controller issues an activation signal to power up the secure element or the resource entity prior to initiation of the upcoming secure transaction. Thus, power can be conserved without introducing a transaction-processing latency.

Speculative activation for secure element usage

A method of emotive autography includes calculating a plurality of classifiers associated with an individual user. Each of the classifiers indicates a preference of the user for an associated type of multimedia content. Multimedia data is received including video data, audio data and/or image data. The multimedia data is divided into semantically similar segments. A respective preference score is assigned to each of the semantically similar segments by use of the classifiers. The semantically similar segments are arranged in a sequential order dependent upon the preference scores. An emotive autograph is presented based on the semantically similar segments arranged in the sequential order.

System architecture for universal emotive autography

Techniques related to stereo image correspondence are discussed. Such techniques may include determining a filtered cost volume for stereo images using phase domain based costs and selecting disparity values for pixel locations based on the filtered cost volume. The filtered cost volume may be generated based on phase matching costs in single or multi-resolution.

Stereo image matching by shape preserving filtering of a cost volume in a phase domain

In one embodiment an electronic device comprises a display, a motion sensor, one or more wireless communication devices, and logic configured to receive, in the controller, data indicating that the controller is in motion, determine a velocity of the controller, and activate a first location service to determine a coarse location of the controller when the velocity of the controller falls above a predetermined threshold for a predetermined period of time. Other embodiments may be described.

Context aware geofencing

Embodiments of encoding input data into parity data in mechanisms are described generally herein. Other embodiments may be described and claimed.

Efficient CTC encoders and methods

A system and method is provided for traffic management and regulation in a packet-based communication network, the system and method facilitating proactive, discriminating congestion control on a per flow basis of packets traversing the Internet via use of a Weighted Random Early Detection (WRED) algorithm that monitors the incoming packet queue and optimizes enqueuing or discard of incoming packets to stabilize queue length and promote efficient packet processing. During optimized discard conditions, the system and method discern a relative priority among incoming packets, distribute packets with a relatively high priority and discard packets with a relatively low priority. Additionally, packet traffic are policed and discarded according to packet type, quantity or other predetermined criteria. The present invention performs in periodic mode, demand mode or both, and can be implemented as a hardware solution, a software solution, or a combination thereof.

Single cycle weighted random early detection circuit and method

A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. One or more numbers in the floating point format are converted to the integer format and placed in a register of a second set of architectural registers in a packed format. Conversion from integer format to floating point format is performed in a similar manner. A floating point arithmetic apparatus is described that provides for converting a plurality of numbers between integer formats and a floating point formats, further providing for conversion operations that require a greater data path width than floating-point arithmetic operations.

Method and apparatus for floating point operations and format conversion operations

The present invention provides a unique system and method for optimizing packet processing flow in a communications network by minimizing latency associated with packet-forwarding eligibility determinations. The present invention employs a speculative scheme with automatic recovery, including a two-way multithreaded implementation designed to overcome the aforementioned latency issue, including the functionality of enqueuing an incoming packet in both packet memory and a cut through buffer; determining the packet's eligibility for cutting through the buffer; and based on the determination, rolling back the unsuccessful process.

Recoverable cut-through buffer and method

A floating point arithmetic apparatus for converting numbers between an integer format and a floating point format, wherein a conversion operation requires a greater data path width than a conversion operation. The apparatus comprises right shift circuitry that receives a number in the floating point format, wherein the right shift circuitry includes additional register positions to accommodate a shift beyond a data path width required by an arithmetic operation.

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Fremont, CA, United States of America

Prasad Modali