Xilinx, Inc.

Prasad L Sastry

Steven P Young

Ahmad R Ansari

Kameswara K Rao

Derek R Curd

Stephen M Douglass

Robert Yin

Mehul R Vashi

Napoleon W Lee

Sholeh Diba

Mihai G Statovici

A data processing system having a user configurable memory controller, one or more local block RAMs, one or more global block RAMs and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the global block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. The number of wait states of the local block RAM is also user selectable. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

User configurable memory system having local and global memory blocks

An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

Programmable logic device with configurable power supply

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Milpitas, CA, United States of America

Prasad L Sastry