International Business Machines Corporation

Prasad Bhosale

Chih-Chao Yang

Michael Rizzolo

Lawrence Alfred Clevenger

Nicholas Anthony Lanzillo

Raghuveer Reddy Patlolla

Injo Ok

Terry Allen Spooner

Cornelius Brown Peethala

Kevin W Brew

Nicole A Saulnier

Hari Prasad Amanapu

Ruilong Xie

Junli Wang

Theodorus E Standaert

Nicolas J Loubet

Dechao Guo

Julien Frougier

Lars W Liebmann

Balasubramanian Pranatharthiharan

Son Van Nguyen

Alfred Grill

Takeshi Nogami

Benjamin David Briggs

Ruqiang Bao

Christian Lavoie

Rudy J Wojtecki

Andrew Herbert Simon

Hosadurga K Shobha

Donald Francis Canaperi

John Christopher Arnold

Huai Huang

James John Kelly

Adra Carr

Iqbal Rashid Saraf

James Jay McMahon

Devika Sil

Steven Michael McDermott

Nicholas V LiCausi

Semiconductor devices including a super via connection between levels are provided. The semiconductor device can include a first interlevel dielectric layer, a back-end-of-line (BEOL) interconnect structure disposed in the first interlevel dielectric layer, a second interlevel dielectric layer disposed on a first portion of the first interlevel dielectric layer, a third interlevel dielectric layer disposed on the second interlevel dielectric layer, and a super via disposed on a second portion of the first interlevel dielectric layer, wherein a first end of the super via is connected to the BEOL interconnect structures and wherein a second end of the super via opposite the first end of the super via is a distance from the first interlevel dielectric layer larger than a height distance of the second interlevel dielectric layer.

BEOL interconnect subtractive etch super via

Embodiments of the invention provide self-assembled monolayers (SAM) formulations and cleaning to promote quick depositions. A hydrogen-based plasma clean is performed on a structure, the structure including a metal layer and a dielectric layer. A self-assembled monolayers (SAM) solution is dispensed on the structure, the SAM solution including SAMs and a solvent, the SAMs being configured to assemble on the metal layer. The structure is rinsed with a rinse solution including the solvent.

Sam formulations and cleaning to promote quick depositions

Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

Gate-cut and separation techniques for enabling independent gate control of stacked transistors

Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.

Rework for metal interconnects using etch and thermal anneal

A method for forming a phase-change memory cell includes depositing a metal layer over a wafer such that the metal layer covers connection structures of the wafer. The method further includes removing a portion of the metal layer such that the connection structures of the wafer remain covered by a remaining portion of the metal layer. The method further includes forming a phase-change memory stack on a stack area of the remaining portion of the metal layer. The method further includes removing the remaining portion of the metal layer except in the stack area.

Phase change memory cell galvanic corrosion prevention

A semiconductor structure may include a heater surrounded by a second dielectric layer, a projection liner on top of the second dielectric layer, and a phase change material layer above the projection liner. A top surface of the projection liner may be substantially flush with a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Phase change memory cell with a projection liner

A semiconductor structure includes an interlayer dielectric layer, a first set of back-end-of-line interconnect structures disposed in the interlayer dielectric layer, and a second set of back-end-of-line interconnect structures at least partially disposed in the interlayer dielectric layer. Each of the first set of back-end-of-line interconnect structures has a first width and a first height providing a first aspect ratio. Each of the second set of back-end-of-line interconnect structures has a second width and a second height providing a second aspect ratio different than the first aspect ratio. The second width is greater than the first width, and the second height is different than the first height.

Back-end-of-line interconnect structures with varying aspect ratios

An example operation may include one or more of identifying a current tool configuration used by a tool device to construct semiconductor devices, retrieving a smart contract stored in a blockchain to identify whether an updated tool configuration exists, responsive to identifying the updated tool configuration, transmitting an update that includes the updated tool configuration to the tool device, and responsive to receiving the updated tool configuration at the tool device, initiating construction of the semiconductor devices.

Semiconductor tool matching and manufacturing management in a blockchain

A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.

Automated method for integrated analysis of back end of the line yield, line resistance/capacitance and process performance

The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

Interconnect with self-forming wrap-all-around barrier layer

Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein the intervening metallization level (MX+1) is electrically isolated from the skip via. Cap layers in the metallization levels are pre-patterned to provide openings therein generally corresponding to locations of the skip via structure prior to high aspect ratio etching to form the skip via structure.

Skip via for metal interconnects

A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.

Bottom electrode for MRAM applications

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Albany, NY, United States of America

Prasad Bhosale