Hewlett-packard Company

Idea Corporation

Oracle Systems Corporation

Instantis, Inc.

Prasad A Raje

Paolo Faraboschi

Rajiv Gupta

Jonathan Kent Ross

Achmed Rumi Zahir

Paul G Emerson

Sunil Saxena

Joseph A Fisher

Cary Coutant

Carol Thompson

Stuart C Siu

According to one aspect of the present invention, a method is provided in which a form is received from an author. A parsing function is performed to extract attribute information with respect to various form elements contained in the form. A user interface is presented to the author to allow the author to configure a set of actions that are to be performed in processing the submissions of the form.

Automated creation and maintenance of programs to process internet form related submissions

A register file organization for a pipelined microprocessor is shown which includes a pipestage register interposed a global bit line and a register cell array of the register file in order to separate the delay associated with driving the global bit line, and devices attached to the global bit line, into a separate pipestage. Another register file organization is shown which includes a pipestage register that is interposed a register cell array and a decoder, which selects a register in the register cell array responsive to an instruction in an instruction register, to separate the decoder function and register cell array access times into different pipestages. The two approaches can be combined to separate the delay associated with the decoder, register cell array and global bit line into different pipestages in order to reduce the pipestage cycle time toward a fundamental minimum for pipelined computer architecture.

High speed register file organization for a pipelined computer

A computer-implemented method of switching contexts in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) to exchange information, in one of instruction execution dependent and independent modes between the second portion and the storage area. The computer implemented method of switching contexts includes the following steps: It is determined whether an interrupt occurred; a first register (IFM) configured to store a content of a second register (CFM) is invalidated, the CFM is configured to store control information related to the first portion; it is determined whether an interrupt handler needs to access the RS; and if so, the IFM is validated, the content of the CFM is copied to the IFM, and RSE is caused to exchange information between both the first and second portions of the RS and the storage area. On return from interruption, if IFM is validated, CFM is restored from IFM else CFM remains unchanged. The COVER instruction enables lightweight interrupt handling in a processor with a Register Stack.

Cover instruction and asynchronous backing store switch

A CPU having a cluster VLIW architecture is shown which operates in both a high instruction level parallelism (ILP) mode and a low ILP mode. In high ILP mode, the CPU executes wide instruction words using all operational clusters of the CPU and all of a main instruction cache and main data cache of the CPU are accessible to a high ILP task. The CPU also includes a mini-instruction cache, a mini-instruction register and a mini-data cache which are inactive during high ILP mode. An instruction level controller in the CPU receives a low ILP signal, such as an interrupt or function call to a low ILP routine, and switches to low ILP mode. In low ILP mode, the main instruction cache and main data cache are deactivated to preserve their contents. At the same time, a predetermined cluster remains active while the remaining clusters are also deactivated. The low ILP task executes instructions from the mini-instruction cache which are input to the predetermined cluster through the mini-instruction register. The mini-data cache stores operands for the low ILP task. The separate mini-instruction cache and mini-data cache along with the use of only the predetermined cluster minimizes the pollution of the main instruction and data caches, as well as pollution of register files in the deactivated clusters, with regard to a task executing in high ILP mode.

Apparatus and method for efficient switching of CPU mode between regions

A microprocessor is provided which includes a power control register for controlling the rate of execution and therefore the power consumption of individual functional units. The power control register includes a plurality of fields corresponding to the functional units for storing values that control the power consumption of each. The power control register fields can be set by software which has the much greater ability to look out into the future to determine whether the functional units will be required. The functional units are responsive to the corresponding power control register field to adjust their rate of execution responsive to the value stored therein. The rate of execution can be controlled in a number of different ways: dividing down the clock; removing power to the functional unit; disabling the sensor and/or buffer driver of one or more of the ports in a multi-ported RAM; removing data from the functional unit; and changing the data bus width responsive to the control register field. The microprocessor also includes a latency control register which assures that the functional unit is operational after the functional unit is placed from a low power state to a more fully operational state by changing the corresponding field in the power control register.

Microprocessor having software controllable power consumption

A method and apparatus for compacting VLIW instructions in a processor having multiple functional units and including a buffer for storing compacted instructions, wherein NOP codes are eliminated from the compacted instruction and each compacted instruction includes words which contain an operation code directing the operation of one of the functional units, a dispersal code, and a delimiter code, wherein an alignment circuit parses each compacted instruction from the buffer based upon the delimiter codes of the words and aligns the compacted instruction in an alignment buffer and a dispersal circuit transfers each word of the compacted instruction stored in the alignment buffer into at least one operational field of a dispersed instruction buffer which stores an executable instruction having an operational field corresponding to each one of the functional units. Another embodiment is also shown which interleaves the bits of a buffer, alignment circuit, alignment buffer, dispersal circuit and dispersed instruction buffer to reduce the circuit area required for expanding the compacted instruction.

Method for storing and decoding instructions for a microprocessor having

An apparatus and method are shown for decoding variable length instructions in a processor where a line of variable length instructions from an instruction cache are loaded into an instruction buffer and the start bits indicating the instruction boundaries of the instructions in the line of variable length instructions is loaded into a start bit buffer. A first shift register is loaded with the start bits and shifted in response to a lower program count value which is also used to shift the instruction buffer. A length of a current instruction is obtained by detecting the position of the next instruction boundary in the start bits in the first register. The length of the current instruction is added to the current value of the lower program count value in order to obtain a next sequential value for the lower program count which is loaded into a lower program count register. An upper program count value is determined by loading a second shift register with the start bits, shifting the start bits in response to the lower program count value and detecting when only one instruction remains in the instruction buffer. When one instruction remains, the upper program count value is incremented and loaded into an upper program count register for output to the instruction cache in order to cause a fetch of another line of instructions and a `0` value is loaded into the lower program count register. Another embodiment of the present invention includes multiplexors for loading a branch address into the upper and lower program count registers in response to a branch control signal.

Method and apparatus for sequencing and decoding variable length

A high frequency circuit using output drivers with tri-state sections. The plurality of output drivers are connected to an output transmission line. Each driver has a pull-up section, a pull-down section and a tri-state section. Each tri-state section has a low impedance and a high impedance state. Its low impedance state serves to match the impedance of the output transmission line. Its high impedance state isolates its driver from the output transmission line.

Output drivers in high frequency circuits

An optimum ratio relating the characteristic dimensions of the MOS pull-up and the MOS pull-down devices of a logic circuit with one or more bipolar devices connected to an output of the circuit. This optimum ratio substantially minimizes the propagation delay of the circuit. The first preferred embodiment is shown in a BiNMOS circuit, and the second preferred embodiment is shown in a BiCMOS circuit.

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Fremont, CA, United States of America

Prasad A Raje