Intel Corporation

Prantik K Nag

Stephen R Mooney

Joseph T Kennedy

Chaiyuth Chansungsan

Shekhar Yeshwant Borkar

Edward Allyn Burton

Yongping Fan

Suresh S Chittor

Jeffrey E Smith

Jerry G Jex

Suneeta Sah

Hong H Chan

Keith-Michael W Self

Joseph Ku

An output buffer generates an output signal having a plurality of low-to-high (LH) and high-to-low (HL) signal transitions, with each of the signal transitions having a clock-to-output delay. A pre-driver having a first and a second stage generates a reshaped waveform to trigger the LH and HL signal transitions of the output signal, with the first stage generating an initial waveform and the second stage modifying the initial waveform to generate the reshaped waveform based at least in part on a feedback reflective of a difference in the clock-to-output delays of the LH and HL signal transitions.

Output buffer with adjustment of signal transitions

A bi-directional communication system includes a driver capable of controlling a slew rate of transmitted data signals. Impedance matching can be provided to match an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. The data receiver circuit can adjust a reference voltage in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.

Slew rate control circuit

A method and apparatus of selectively flushing a conflicted write transaction from a memory controller. According to the method, a new transaction is received that identifies a memory address to which the transaction is directed. It is determined whether an address of the new transaction matches an address of any previously queued transaction. When a match occurs, the one previously queued transaction that matches the new transaction is flushed from queue.

Selective conflict write flush

A unidirectional point-to-point communication apparatus for communicating messages between two computing resources irrespective of the phase of the messages, length of a communication path between the two computing resources and internal speed of the two computing resources. The communication apparatus has a high speed communication bus coupling a transmitter and a receiver for transmitting the messages from the transmitter to the receiver. A high speed communication clock is coupled to the bus and the receiver for timing the messages transmitted on the high speed communication bus between transmitter and the receiver. A large data buffer is coupled to the high speed communication bus after the receiver for storing messages transmitted between the transmitter and the receiver. A buffer accessing circuit is coupled to the buffer for referencing write locations to store the messages received from the transmitter over the communication bus, and for referencing read locations for reading the messages out of the buffer by the receiver. Finally, a delay locked loop circuit is coupled to the communication bus, the buffer accessing circuit and the buffer for providing the proper set-up and hold time requirements for the messages transmitted on the communication bus from the transmitter and storing the messages in the buffer.

Point-to-point phase-tolerant communication

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Hillsboro, OR, United States of America

Prantik K Nag