Xilinx, Inc.

Pranjal Joshi

Amit Kumar

Sebastian Turullols

Sonal Santan

Ravi Nagarajarao Kurlagunda

Ravinder Sharma

Ch Vamshi Krishna

Cheng Zhen

Kaustuv Manji

Min Ma

Manjunath Chepuri

Himanshu Choudhary

Ravi N Kurlagunda

A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

High throughput circuit architecture for hardware acceleration

Growing community of inventors

San Jose, CA, United States of America

Pranjal Joshi