International Business Machines Corporation

Globalfoundries Inc.

Elpis Technologies Inc.

Praneet Adusumilli

Oscar Van Der Straten

Alexander Reznicek

Chih-Chao Yang

Takashi Ando

Reinaldo Ariel Vega

Zuoguang Liu

Cheng Chi

Christian Lavoie

Hemanth Jagannathan

Jianshi Tang

Keith E Fogel

Ahmet Serkan Ozcan

Veeraraghavan S Basker

Emre Alptekin

Tenko Yamashita

Kangguo Cheng

Adra Carr

Balasubramanian Pranatharthiharan

Koichi Motoyama

Joshua M Rubin

Ruilong Xie

Chun-chen Yeh

Shogo Mochizuki

Oleg Gluschenkov

Dechao Guo

Shom Ponoth

Rajasekhar Venigalla

Chun Wing Yeung

Vimal Kumar Kamineni

David S Wolpert

Jie Yang

Shanti Pancharatnam

Juntao Li

Carl John Radens

Bahman Hekmatshoartabari

Keith Kwong Hon Wong

Huiming Bu

Kevin W Brew

Matthew Joseph BrightSky

Miaomiao Wang

Joseph F Maniscalco

Mark V Raymond

Chengyu Charles Niu

Wonwoo Kim

Jean L Sweet

Bruce Bennett Doris

Guy M Cohen

Josephine B Chang

Vijay Narayanan

Michael A Guillorn

Injo Ok

Martin Michael Frank

Ramachandran Muralidhar

Robert L Bruce

Nicole A Saulnier

Alessandro Cesare Callegari

James John Kelly

Nicolas L Breil

Balasubramanian S Pranatharthi Haran

Iqbal Rashid Saraf

Changhwan Choi

Domingo A Ferrer

Karthik Yogendra

Arthur Gasasira

Neal A Makela

Anirban Chandra

An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate. The decoupling capacitor is also connected to a second gate. As such, the decoupling capacitor separates the first gate from the second gate. The decoupling capacitor may include a dielectric liner within a gate cut trench and a ferroelectric material over the dielectric liner. A second power rail may be connected to the decoupling capacitor by way of the second gate. The first gate and the second gate may be inline with respect thereto.

Decoupling capacitor inside gate cut trench

A ring-shaped heater, system, and method to gradually change the conductance of the phase change memory through a concentric ring-shaped heater. The system may include a phase change memory. The phase change memory may include a bottom electrode. The phase change memory may also include a ring-shaped heater patterned on top of the bottom electrode, the ring-shaped heater including: a plurality of concentric conductive heating layers, and a plurality of insulator spacers, where each insulator spacer separates each conductive heating layer. The phase change memory may also include a phase change material proximately connected to the ring-shaped heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

Phase change memory with concentric ring-shaped heater

A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.

Phase change memory with conductive rings

A memory, system, and method to improve integration density while maintaining thermal efficiency through a phase change memory cell with a superlattice based thermal barrier. The phase change memory may include a bottom electrode. The phase change memory may also include an active phase change material. The phase change memory may also include a superlattice thermal barrier proximately connected to the active phase change material. The phase change memory may also include a top electrode proximately connected to the superlattice thermal barrier. The system may include the phase change memory cell. The method for forming a phase change memory may include depositing an active phase change material on a bottom electrode. The method may also include depositing a superlattice thermal barrier proximately connected to the active phase change material. The method may also include depositing a top electrode proximately connected to the superlattice thermal barrier.

Phase change memory cell with superlattice based thermal barrier

A memory device is provided. The memory device includes a main feature disposed beneath a surface of a photolithographic mask. The memory device further includes at least one Sub-Resolution Assistant Feature (SRAF) proximate to the main feature beneath the surface. The main feature has an electrical conductivity based on an area relationship with the at least one SRAF.

Random weight initialization of non-volatile memory array

An approach to forming a semiconductor device where the semiconductor device includes a first power rail with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling capacitor. The semiconductor device includes the first de-coupling capacitor in a first portion of a semiconductor substrate in a first gate cut trench.

A method for manufacturing a phase-change memory device includes providing a substrate including a plurality of bottom electrodes, patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes, depositing a phase-change material over the substrate, implanting one or more of a Ge, Sb and Te in the phase-change material to amorphize at least a portion of the phase-change material inside the pore, planarizing the device to exposed the surface of the substrate, and forming a plurality of top electrodes over the pores, in contact with the phase-change material.

Fill-in confined cell PCM devices

An apparatus includes a first plate, a second plate, a third plate, a ferroelectric dielectric, and a paraelectric dielectric. The ferroelectric dielectric is between the first plate and the second plate such that the first plate, the ferroelectric dielectric, and the second plate form a first capacitor. The paraelectric dielectric is between the second plate and the third plate such that the second plate, the paraelectric dielectric, and the third plate form a second capacitor.

Ferroelectric and paraelectric stack capacitors

A field effect device is provided. The field effect device includes an active gate structure, a gate contact within the active gate structure, wherein the gate contact is the same height as the active gate structure, and a gate cut dielectric on opposite sides of the gate contact and active gate structure.

Gate contact inside gate cut trench

A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.

Multilayer dielectric for metal-insulator-metal capacitor

Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.

CBRAM with controlled bridge location

A method may include forming a bottom electrode in an interlayer dielectric, depositing a liner on top of the bottom electrode, depositing a phase change material layer on top of the liner, wherein a top surface of the liner is in direct contact with a bottom surface of the phase change material layer, and depositing a barrier on top of the phase change material layer, wherein a top surface of the phase change material layer is in direct contact with a bottom surface of the barrier. The barrier may be made of doped phase change material. The forming of the bottom electrode may further include forming a via in the interlayer dielectric, depositing an outer layer along a bottom and a sidewall of the via, depositing a middle layer on top of the outer layer, and depositing an inner layer on top of the middle layer.

Phase change memory cell with a thermal barrier layer

A device includes an electronic component, and the electronic component includes a first pad, a second pad, and a strip connecting the first pad and the second pad. The device further includes a first electrode in contact with the first pad and a second electrode in contact with the second pad. The electronic component is made of a phase change material. At least one of the first electrode and the second electrode is coated with a material that is configured to increase a difference in workfunction between the first electrode and the second electrode.

Phase-change memory device with reduced programming voltage

A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.

Resistive memory with embedded metal oxide fin for gradual switching

A field effect transistor (FET) device is provided. The device includes an isolation region on a support substrate that separates a first back gate from a second back gate, and a gate dielectric layer on a first channel region and a second channel region. The device further includes a conductive gate layer having a work function value and a ferroelectric layer on the gate dielectric layer, wherein the first back gate can adjust a threshold voltage for the first channel region, and the second back gate can adjust a threshold voltage for the second channel region.

Field effect transistor (FET) devices

Growing community of inventors

Albany, NY, United States of America

Praneet Adusumilli