Texas Instruments Corporation

Sap Se

Pranav Kumar

Yogesh Darwhekar

Arpan Sureshbhai Thakkar

Apoorva Bhatia

Srikanth Manian

Sahana Durgam Udaya

Jagdish Chand

Naveen Mahadev

Abhrarup Barman Roy

Subhashish Mukherjee

Jayawardan Janardhanan

Srinivas Theertham

Uday Kiran Meda

Peeyoosh Mirajkar

Raghavendra Reddy

Sonam Sadhukhan

A frequency synthesis circuit includes a first inductor coupled to receive a first input signal at an input frequency, and a second inductor coupled to receive second input signal at the input frequency and out-of-phase relative to the first input signal. The circuit has first and second transistors with control terminals coupled to the first and second inductors, respectively. A first resonant tank of an inductor in parallel with a capacitor is coupled between a power supply terminal and the first transistor. A second resonant tank of an inductor in parallel with a capacitor is coupled between the power supply terminal and the second transistor. The first and second resonant tanks are tuned to a selected harmonic of the input frequency. An injection-locked oscillator has inputs coupled to the first and second transistors.

Transformer-coupled input buffer for frequency synthesis

Mechanisms are disclosed for visualizing and comparing an import and update history of content package objects in an analytic content system. Object to package mapping identifiers corresponding to the content package object are received. A package-identifier object state of a state of the content package object is received corresponding to an imported package associated with a particular package identifier. A modified object state to an original object state is compared prior to re-export of the content package object. The current object state to an original object state of the content package object is compared prior to importing the content package object from the imported package. A visualization of an import history of the content package object is displayed. In response to determining that an issue is present with a most recent import of the one or more content package objects, imports are rolled back to a stable set of objects.

Exploratory analysis of content package objects

Object-based transportation between tenants may provide advantages over persistence layer-based transportation on a cloud platform in situations where persistence layer storage space is limited. Object based transportation involves obtaining a selection from the target tenant application of a set of objects from the plurality of objects and determining objects identifiers for each of the selected set of objects. For each object in the selected set of objects, a request is sent to a source tenant. The requests includes the corresponding object identifier for that object. Corresponding object data is received from the source tenant. At least a portion of the corresponding object data is stored in a target tenant database. An existing object may be updated or a new object may be created.

Object-based transportation across tenants

In an example, a system is adapted to be coupled to a load device having a load clock. The system includes a clock generation device with a pin. The system also includes a capture circuit coupled to the pin and operable to sample a value at the pin. The system includes a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, where the D flip-flop is operable to provide, at the output, a system reference event (SYSREF) signal to align the load clock to the clock, based at least in part on the value at the pin.

Glitch-free synchronization and SYSREF windowing and generation scheme

A circuit for subharmonic detection includes in-phase and quadrature mixers, first and second filters, and a processing circuit. The in-phase mixer has a first mixer input and a first mixer output. The quadrature mixer has a second mixer input and a second mixer output, the first mixer input coupled to the second mixer input. The first filter circuit has a first filter input and a first filter output, the first filter input coupled to the first mixer output. The second filter circuit has a second filter input and a second filter output, the second filter input coupled to the second mixer output. The processing circuit has a first input and a second input, the first input of the processing circuit coupled to the first filter output, the second input of the processing circuit coupled to the second filter output. The processing circuit is configured to detect a subharmonic component of a wave at the first mixer input and the second mixer input using a first direct current (DC) component at the first input of the processing circuit and a second DC component at the second input of the processing circuit.

Subharmonic detection and cancelation

An example apparatus includes: a first flip flop having a first output and a first reset input, a second flip flop having a first data input, a second output, and a second reset input, the second reset input coupled to the first reset input, a logic gate having a first logic input, a second logic input, and a first logic output, the first logic input coupled to the first output and the second logic input coupled to the second output, a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic output and the delay cell output coupled to the first reset input and the second reset input, and pulse swallowing circuitry having a circuitry input and a circuitry output, the circuitry input coupled to the second output and the circuitry output coupled to the first data input.

Methods and apparatus to implement pulse swallowing circuitry in a phase frequency detector

A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

Frequency synthesizer

A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.

Phase error reduction in a receiver

A circuit includes a first bipolar junction transistor (BJT) including a first base, a first collector, and a first emitter, the first collector connected to a first supply voltage node and a second BJT including a second base, a second collector, and a second emitter, the second collector connected to the first emitter at an output node. The circuit also includes a capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT and the second capacitor terminal connected to a second supply voltage node. A current source device is also included that is connected in parallel with the capacitor.

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Hatia, India

Pranav Kumar