Intel Corporation

Micron Technology Incorporated

Agere Systems Inc.

Sk Hynix Nand Product Solutions Corp.

Intel Ndtm US LLC

Other

Lodestar Licensing Group LLC

Pranav Kalavade

Krishna Kumar Parat

Shantanu R Rajwade

Akira Goda

Mark Alan Helm

Ravi H Motwani

Shyam Sunder Raghunathan

Ali Khakifirooz

Violante Moschiano

Aliasgar S Madraswala

Charan Srinivasan

Anand S Ramalingam

Rohit Sudhir Shenoy

Aaron S Yip

Xin Guo

Han Zhao

Tommaso Vali

Andrew Bicksler

Andrea D'Alessandro

Khaled Hasnat

Shafqat Ahmed

Han Liu

Toru Tanzawa

Chang Wan Ha

Neal R Mielke

Feng Zhu

Koichi Kawai

Yogesh B Wakchaure

Jun-Fei Zheng

Uday Chandrasekhar

Matthew Goldman

Purval Shyam Sule

Arash Hazeghi

Xiang Yang

Jawad Basit Khan

Kiran Pangal

Paul D Ruby

Doyle W Rivers

Nathan Franklin

David J Pelster

Sagar Upadhyay

Myron Loewen

Iwen Chao

John Michael Hergenrother

Brennan A Watt

Hsiao-Yu Chang

Giulio Giuseppe Marotta

Zion S Kwok

Deepak Thimmegowda

Owen W Jungroth

Carmine Miccoli

Kristopher H Gaewsky

Dale J Juenemann

Marco Domenico Tiburzi

Donia Sebastian

Ning Wu

Hiroyuki Sanda

Ramkarthik Ganesan

Robert Frickey

Ervin T Hill

Tarek Ahmed Ameen Beshari

Prasanna Srinivasan

Sung-Taeg Kang

Ercole Di Iorio

Trupti Bemalkhedkar

Karthikeyan Ramamurthi

Bharat M Pathak

Naveen Prabhu Vittal Prabhu

Binh N Ngo

Xin Sun

Binh Ngo

Golnaz Karbasian

Bharat Pathak

Hoon Cho

Christian Mion

Rifat Ferdous

Andrea D'alessandro

Purval S Sule

Shantanu Rajwade

An embodiment of an apparatus may include NAND memory organized as two or more memory planes and a controller communicatively coupled to the NAND memory, the controller including circuitry to provide synchronous independent plane read operations for the two or more memory planes of the NAND memory. Other embodiments are disclosed and claimed.

Synchronous independent plane read operation

Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.

Configuration of a memory device for programming memory cells

A method is described. The method includes performing the following on a flash memory chip: measuring a temperature of the flash memory chip; and, changing a program step size voltage of the flash memory chip because the temperature of the flash memory chip has changed.

Flash memory chip that modulates its program step voltage as a function of chip temperature

Systems, apparatuses and methods may provide for technology that boosts strings of a plurality of NAND sub-blocks to a pass voltage, deboosts a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks, and simultaneously programs the first subset while a second subset of the boosted strings remain at the pass voltage. In one example, to boost the strings of the NAND sub-blocks, the technology applies the pass voltage to selected and unselected wordlines that are connected to the NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the NAND sub-blocks.

Simultaneous programming of multiple sub-blocks in NAND memory structures

In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.

Method and apparatus for improving write uniformity in a memory device

A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2−1, and Ln being one of 2threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV

Cache processes with adaptive dynamic start voltage calculation for memory devices

Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. The first density and the second density are different from one another.

Variable error correction codeword packing to support bit error rate targets

Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.

Apparatuses, systems, and methods for heating a memory device

Apparatus, systems, or methods for a memory array having a plurality of word lines. A word line includes at least one word line plate, and the word line plate comprises a first material with a first resistivity. An edge of the word line plate is recessed and filled with a second material having a second resistivity that is lower than the first resistivity. As a result, the total resistance of the word line may be reduced compared to a word line using only the first material with the first resistivity. Other embodiments may also be described and claimed.

Resistance reduction for word lines in memory arrays

Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.

Defective bit line management in connection with a memory access

A memory device comprising a memory array; and controller circuitry to apply a first pass voltage to a first plurality of unselected wordlines of the memory array during a string current sensing phase; and reduce the first pass voltage applied to the first plurality of unselected wordlines during a multistrobe sensing phase that follows the string current sensing phase.

String current reduction during multistrobe sensing to reduce read disturb

Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

Method and system for reducing program disturb degradation in flash memory

Growing community of inventors

San Jose, CA, United States of America

Pranav Kalavade