Intel Corporation

Pranav H Mehta

Shreekant S Thakkar

Robert J Greiner

Peter J Ruscito

Derek L Davis

Minda Zhang

Jeff C Morriss

Paul S Gryskiewicz

Lionel S Smith

Nicholas Ong

Robert Wickersheim

Narayanan S Iyer

Jeff C Morris

Narayana S Iyer

A unique processor serial number may be utilized to augment a device key seed stored in a non-volatile memory. In this way, a relatively secure system may be enabled that facilitates renewing the device key. An integrated circuit may include a transport demultiplexer and key logic. The key logic communicates with the processor using a secure protocol. The key logic can generate random numbers that may be hashed with the processor serial number and the device key seed to generate a device key. The device key may be provided to a head end to facilitate secure communications between the head end and the client.

Enabling secure communications with a client

A method and system are disclosed allowing devices to communicate using a highly efficient low pin count bus comprising a set of data lines, a strobe line, and one control line. Command information is transmitted simultaneously with data, the command information being defined by its timing.

Method and system for implementing control signals on a low pin count bus

An apparatus and method for communication between a host CPU and a security co-processor are disclosed, in which a bus having a bi-directional data and command bus, a bi-directional control line, and a uni-directional clock line, is coupled to the CPU and to the co-processor. The bus supports data transfer between the CPU and the co-processor, including read operations and write operations, where each such operation includes a command phase, a data transfer phase, and an error check phase. The CPU and the co-processor have a dual master slave mode wherein either may be master of the bus, while the other is the slave. The bi-directional data and command bus carries command information from the master to the slave during the command phase, and carries data from the master to the slave during the data transfer phase for a write operation, and from the slave to the master for a read operation. The bi-directional control line specifies the start and end of each transfer. The uni-directional clock line synchronously clocks both the bi-directional data and command bus and the bi-directional control line. Data is transferred a packet at a time; each packet consists of an octet of data, which is transferred during 8 clocks. Flow control need only be applied once for each packet of data, and thus, only once per 8 clocks.

Apparatus and method for multiplexing bi-directional data onto a low pin count bus between a host CPU and co-processor

A cryptographic device is implemented in communication with a host processor to prevent the host processor from performing a standard boot-up procedure until a basic input output system (BIOS) code is authenticated. This is accomplished by a cryptographic device which is addressed by the host processor during execution of a first instruction following a power-up reset. The cryptographic device includes a first integrated circuit (IC) device and a second IC device. The first IC device includes a memory to contain firmware and a root certification key. The second IC device includes logic circuitry to execute a software code to authenticate the BIOS code before permitting execution of the BIOS code by the host processor.

Method for BIOS authentication prior to BIOS execution

An interlaced video signal may be combined with a progressive video signal, such as a graphics signal, by converting the interlaced video signal into a progressive signal. A new frame of the converted progressive signal is constructed from each field of the interlaced signal. The graphics signal is interlaced, then combined with the converted progressive signal. The combined signals may then be transmitted to a display, such as a television set. The interlaced video signal, which is transmitted at twice its incoming speed, remains temporally correct so that operations, such as scaling and 3:2 pulldown, may be performed with minimal resulting artifacts. The small amount of memory used to combine the signals may be embedded in the receiver circuitry.

Synchronizing interlaced and progressive video signals

A method and apparatus for configuring the address space of a computer is described. According to the present invention, a computer system has a full address space and includes at least one base unit, at least one expansion unit and a microprocessor core. The microprocessor core issues access addresses. The full address space includes a base address space and an expanded address space. The base address space is addressed by an M bit address and the expanded address space is addressed by an N bit address (N.gtoreq.M). Each base unit is mapped to an address within the base address space, and the base unit address is mirrored in the expanded address space. Each expansion unit is mapped to an address within the expanded address space. An address configuration circuit in the computer system includes an address space remapping circuit for selectively remapping or not remapping base units out of the base address space. The address configuration circuit also includes an expanded space enabling circuit for selectively enabling or disabling the expanded address space. Expansion units are accessible in the expanded address space depending upon whether the expanded address space has been enabled.

Growing community of inventors

Chandler, AZ, United States of America

Pranav H Mehta