Advanced Micro Devices Corporation

Qualcomm Incorporated

Pramod Vasant Argade

Andrew Evan Gruber

Swapnil Pradipkumar Sakharshete

Daniel Nikolai Peroni

Babak Forutanpour

Guofang Jiao

Maxim V Kazakov

Jing Wu

Alexander M Potapov

Andrew J Everitt

Lin Chen

Shriram Ganesh

Milind Nilkanth Nemlekar

Gerald Patrick Joyce, Iii

Chiente Ho

Martin G Sarov

Stewart Griffin Hall

A processing device is provided which comprises memory configured to store data and a processor configured to receive a portion of data of a first matrix comprising a first plurality of elements and receive a portion of data of a second matrix comprising a second plurality of elements. The processor is also configured to determine values for a third matrix by dropping a number of products from products of pairs of elements of the first and second matrices based on approximating the products of the pairs of elements as a sum of the exponents of the pairs of elements and performing matrix multiplication on remaining products of the pairs of elements of the first and second matrices.

Approximation of matrices for matrix multiply operations

A processing device is provided which comprises memory configured to store data and a processor. The processor comprises a plurality of MACs configured to perform matrix multiplication of elements of a first matrix and elements of a second matrix. The processor also comprises a plurality of logic devices configured to sum values of bits of product exponents values of the elements of the first matrix and second matrix and determine keep bit values for product exponents values to be kept for matrix multiplication. The processor also comprises a plurality of multiplexor arrays each configured to receive bits of the elements of the first matrix and the second matrix and the keep bit values and provide data for selecting which elements of the first matrix and the second matrix values are provided to the MACs for matrix multiplication.

Data compressor for approximation of matrices for matrix multiply operations

Techniques for managing register allocation are provided. The techniques include detecting a first request to allocate first registers for a first wavefront; first determining, based on allocation information, that allocating the first registers to the first wavefront would result in a condition in which a deadlock is possible; in response to the first determining, refraining from allocating the first registers to the first wavefront; detecting a second request to allocate second registers for a second wavefront; second determining, based on the allocation information, that allocating the second registers to the second wavefront would result in a condition in which deadlock is not possible; and in response to the second determining, allocating the second registers to the second wavefront.

Dynamically reconfigurable register file

A processing system selectively enables and disables a result lookaside buffer (RLB) based on a hit rate tracked by a counter, thereby reducing power consumption for lookups at the result lookaside buffer during periods of low hit rates and improving the overall hit rate for the result lookaside buffer. A controller increments the counter in the event of a hit at the RLB and decrements the counter in the event of a miss at the RLB. If the value of the counter falls below a threshold value, the processing system temporarily disables the RLB for a programmable period of time. After the period of time, the processing system re-enables the RLB and resets the counter to an initial value.

Selectively enabled result lookaside buffer based on a hit rate

A processor selectively adjusts the precision of data for different functional units. Specified functional units of the processor, such as shader processing unit of a graphics processing unit (GPU) include a zeroing module to store, based on the states of corresponding precision flags, a data value of zero at specified portion of an input and/or output data operand. The functional unit then processes the data including the zeroed portion. Because a portion of the data has been zeroed, the functional unit consumes less power during data processing. Furthermore, the precision flags are set such that the reduced precision of the data does not significantly impact a user experience.

Variable precision computing system

Techniques are disclosed for compressing data. The techniques include identifying, in data to be compressed, a first set of values, wherein the first set of values include a first number of two or more consecutive identical non-zero values; including, in compressed data, a first control value indicating the first number of non-zero values and a first data item corresponding to the consecutive identical non-zero values; identifying, in the data to be compressed, a second value having an exponent value included in a defined set of exponent values; including, in the compressed data, a second control value indicating the exponent value and a second data item corresponding to a portion of the second value other than the exponent value; and including, in the compressed data, a third control value indicating a third set of one or more consecutive zero values in the data to be compressed.

Lossless machine learning activation value compression

A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.

Uniform predicates in shaders for graphics processing units

At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value.

Emulation of fused multiply-add operations

Methods, devices and systems enable prioritizing mobile device access to a communication network during periods of reduced network availability, such as during emergency situations. The mobile device may be configured to detect the existence of an emergency situation locally, on the mobile device. Upon recognizing an emergency situation the mobile device may collect information from various components and/or sensors of the mobile device. Using the collected information, the mobile device may compute a priority for accessing the communication network. Using the computed priority, the mobile device may attempt to access the communication network in a manner that staggers access attempts among all mobile devices to reduce network congestion.

Growing community of inventors

San Diego, CA, United States of America

Pramod Vasant Argade