Other

Pramod Sharma

Narayanan Kannan

Madhur Kashyap

A method of estimating capacitive cell load of cells in an integrated circuit (IC) design uses first maximum capacitive load values Cin calculating risk of electromigration failure in cells of the IC design. Cis saved for a cell whose risk of electromigration failure is acceptable. For a failed cell, a revised maximum capacitive load value Cis reduced as the ratio of an actual current Irelative to the electromigration current limit Iin the weakest element of the cell. A revised actual current Iis obtained as a function of transition times with C. Cis saved for the cell if Iis less than I. Otherwise the steps of calculating Cand Iare re-iterated. Cis reduced relative to Cfor the first iteration and is further reduced relative to its previous value Cfor subsequent iterations.

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Noida, India

Pramod Sharma