Intel Corporation

Pramod Kolar

Gunjan H Pandya

John Reginald Riley

Uddalak Bhattacharya

Eric A Karl

Zheng Guo

Wei-Hsiang Ma

Yih Wang

Kevin X Zhang

Jaydeep P Kulkarni

Fatih Hamzaoglu

Farhana Sheikh

Karthik Subramanian

Yong-Gee Ng

Ankit Sharma

Hyunwoo Nho

Subho Chatterjee

A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

Negative bitline write assist circuit and method for operating the same

In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.

Capacitive wordline boosting

An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.

Read and write apparatus and method for a dual port memory

A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.

Operation aware auto-feedback SRAM

In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

Dual-port static random access memory (SRAM)

Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.

Adaptive and dynamic stability enhancement for memories

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Hillsboro, OR, United States of America

Pramod Kolar